Hardware Debug And Validation Engineer Jobs

Job Details: Job Description: Position Overview: As a Platform Hardware Design Engineer, you will contribute to the end-to-end development of advanced platform hardware, translating platform level requirements into circuit and component level specifications and ultimately into high quality board designs. You will work across the hardware development lifecycle, including architecture and requirements definition, component selection, schematic design, PCB implementation, design reviews, board fabrication and assembly support, power-on, bring-up, debug, validation, and delivery. This is a hands-on engineering role for candidates who enjoy solving complex hardware problems and working across disciplines to turn system requirements into reliable, manufacturable hardware. Our Business Group You will be joining the Silicon and Platform Engineering Group (SPE), an organization at Intel committed to advancing Intel's mission of delivering world class silicon and platform solutions. The group focuses on developing integrated systems that align with customer needs and support Intel's broader goals of leadership in technology innovation. SPE collaborates across diverse domains to ensure Intel platforms meet performance, reliability, and scalability requirements. Our work sits at the intersection of silicon, board hardware, firmware, validation, signal and power integrity, mechanical and thermal engineering, PCB technology, manufacturing, and system integration. Our hardware engineers have a broader responsibility than executing an individual design. They help establish platform architecture, guide implementation, identify and qualify appropriate hardware solutions, provide technical leadership during board power-on and debug, and lead resolution of schematic, layout, SI/PI, and hardware issues. Key Responsibilities Platform and Board Design • Translate platform level requirement

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Key Responsibilities Validation Execution Lead end‑to‑end Validation Run execution in a high‑pressure, fast‑paced environment , ensuring on‑schedule starts/completions , risk‑aware re‑plans , and efficient material usage . Own time‑bound data crunching pipelines (automated log parsing, metrics aggregation, anomaly ranking) and deliver decision‑ready summary reports and sightings by agreed Cycle Time. Guarantee coverage completeness across Validation flows; drive Hot/Cold corners , screen , timing boundary coverage, and evidence‑backed closure . Platform Leadership Develop and debug test programs on ATEs like Advantest and In-house ATE; enforce code quality, reviews, and release discipline. Align hardware configs ( handler, socket, loadboard, probe card ) to test intent and throughput targets. Advanced Analysis, Verilog Simulation & Automation Perform power/thermal characterization ; correlate IDD/thermal data with performance/reliability; author recommendations for content changes and silicon fixes. Architect and execute Verilog simulations (bench cre

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Lead DFT Engineer Job Description: Developing silicon for edge-to-cloud computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities: Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST. Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis . Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time. Technical Requirements: Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Bachelor’s degree in a related field. Tools:

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Description : Lead DFT Engineer (Edge Computing) Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST. Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis . Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time. Technical Requirements Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Tools: Mastery of industry-standard

Why RoboForce RoboForce is an AI robotics company developing Physical AI–powered Robo-Labor for dull, dirty, and dangerous work. The company’s robots are engineered for demanding industrial environments, with a focus on real-world deployment and scalability. We are looking for a motivated Robotics Electrical Engineering Intern for Fall/Winter 2026 to join our team. This role is a hands-on opportunity to bridge the gap between hardware design and embedded software. You will be instrumental in bringing our in-house electronics boards to life by debugging hardware circuits and developing the firmware that drives them. You will work alongside a team of world-class researchers and engineers on ambitious, real-world problems at the intersection of foundation models, decision-making, and robotics. This is an opportunity to help shape core research directions, build cutting-edge systems, and contribute to work with strong potential for publication at top-tier conferences. Responsibilities Perform circuit validation including power-on tests, signal integrity checks, and continuity testing Troubleshoot hardware issues using oscilloscopes, multimeters, and logic analyzers Develop, test, and maintain embedded firmware for Arduino (C++) and STM32 (C) platforms using open-source libraries Implement and debug communication protocols including CAN bus , I2C, SPI, and UART Validate communication protocols with Linux-based environments Ensure reliability and robustness of firmware in real-world conditions Manage end-to-end documentation, turning complex debugging and firmware details into clear, actionable guides for engineers. Requirements Currently pursuing a BS, MS or PHD in Electrical Engineering, Computer Engineering, or a related field Proficiency with the Arduino ecosystem and experience or strong interest in STM32 (HAL/LL or STM32CubeIDE) Understanding of CAN bus architecture and messaging Hands-on experience with lab tools (oscilloscopes, digital multimeters, function genera

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We're seeking a System Software Engineer to join our First-Party Hardware team. In this role, you will design, build, integrate, and validate low-level system software for the manageability and health of OpenAI's first-party AI hardware systems. You will work across BMC, Linux, firmware interfaces, automation infra, boot and recovery, hardware diagnostics, telemetry, host and platform drivers, network software interfaces, and manufacturing and fleet readiness. A major part of this role is owning the acceptance path for partner-delivered system software: defining requirements, reviewing code and artifacts, reproducing builds, building tests, pushing fixes, and producing the evidence needed for launch decisions. This role is hands-on and high-ownership. You will write and review low-level software, debug issues across hardware and software boundaries, build infra and automation to test and manage devices in lab, guide partner deliverables, build validation evidence, and help carry platforms from bring-up through production deployment. Location: San Francisco, CA (Hybrid: 3 days/week onsite) Relocation assistance available. In this role, you will: Design, develop, and maintain low-level firmware and system software for first-party AI hardware manageability, including BMC software, Redfish services, gNMI telemetry, firmware update and recovery flows, BIOS/UEFI interactions, platform drivers, and hardware diagnostics. Own integration and acceptance of partner and ve

We’re looking for a Systems Engineer to join our globally distributed Trading Infrastructure team. This is an end-to-end role: you will work on full-stack infrastructure tasks — from new site/provider setups and environment bring-up to validation testing, troubleshooting, and performance bottleneck analysis. You will collaborate closely with vendors, network and hardware engineers and take ownership of delivering reliable production-ready setups What You’ll be doing Deliver end-to-end infrastructure setups across regions/colocations: bring-up, validation, and go-live readiness Own the systems side of the stack: Linux servers, OS baseline, automation, configuration, and performance tuning Run and improve testing/validation: connectivity checks, load/performance tests, failure testing, and readiness checklists Participate in investigation of complex issues and bottlenecks across layers (OS/kernel/drivers/dependencies) and drive fixes with network/hardware peers and 3rd party vendors Build repeatable automation and rollout playbooks (Terraform/Ansible, scripting, standards) Improve observability: metrics/logs, dashboards, alert tuning, and latency/performance baselines Strengthen operations: runbooks, incident reviews (RCA), change hygiene, and documentation Participate in scheduled on-call rotations to support trading infrastructure and incident response. What we look for in you: Hands-on production experience with Linux and systems troubleshooting Ability to debug across layers and coordinate effectively with network/hardware engineers Solid networking fundamentals (TCP/IP, DNS, routing basics, MTU, packet loss/jitter symptoms) Automation mindset: bash/Python; Terraform/Ansible experience is a plus Strong written and verbal communication (clear status updates and documentation) Passion for technology and continuous learning Nice-to-Have: Low-latency / performance tuning experience (CPU/IRQ affinity, NIC tuning, etc.). Colocation / provider coordination ex

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As a Hardware Manufacturing Test Engineer at Everpure, you will spearhead manufacturing test enablement for our next-generation enterprise hardware platforms from New Product Introduction (NPI) through high-volume production ramp. Operating with high autonomy, you will design robust test strategies and collaborate cross-functionally with Firmware, Diagnostics, and global factory teams to deliver market-ready, high-yield hardware infrastructure. Your expertise will directly optimize manufacturing throughput, improve release quality, and accelerate the global deployment of the industry-defining Everpure Platform. WHAT YOU'LL DO Own NPI & Sustaining Test Readiness: Drive end-to-end manufacturing test strategy, test sequence definition, and coverage validation for multiple hardware infrastructure variants to ensure seamless factory execution and build readiness. Lead Debug & Yield Optimization: Independently lead technical triage and resolve complex system-level test fallout during critical build phases, analyzing failure paretos to isolate root causes across hardware, firmware, and test infrastructure. Scale Test Architecture & Frameworks: Enhance and standardize the Design for Manufacturing (DFM) hardware test architecture by deploying reusable automation frameworks and consolidating test execution into shared platforms to minimize factory cycle times. Drive Vendor & Cross-Functional Alignment: Colla

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role Overview The ASIC Test Engineer is responsible for test program development, silicon validation, yield analysis, and production test optimization for advanced ASIC/SSD controller products. This role supports both NPI and HVM phases, driving fast ramp, robust quality, and cost-effective test solutions across wafer sort and final test. Key Responsibilities Develop and debug ATE test programs for wafer sort and final test (probe to package) to support silicon bring-up and production ramp. Drive yield analysis, failure characterization, and root cause investigation to accelerate yield improvement and ensure product quality. Collaborate with design, product engineering, reliability, and OSAT teams to resolve test and silicon issues across the product lifecycle. Optimize test coverage, test time (TTR), and cost through test content development, guardband tuning, and screening strategy improvements. Support hardware bring-up including probe cards, load boards, and tester configurations to ensure stable manufacturing operations. Enable efficient NPI execution by developing scalable test solutions and improving cycle time from bring-up to HVM. AI/Advanced Data Capability Apply AI/ML and data-driven methodologies to enhance yield analysis, anomaly detection, and failure classification. Leverage AI-assisted tools (e.g., code generation, debug automation, data analytics platforms) to improve engineering productivity and debug cycle time.<br

NVIDIA seeks an exceptional Network Engineer to join the Vertical Verification Group. As a senior engineer, you will contribute to the Vertical Verification work, concentrating on validating and improving complex Ethernet and InfiniBand systems within NVIDIA’s Data Center and HPC environments. You will play a key role in testing advanced networking features, building complex customer-like topologies, and ensuring NVIDIA products meet industry-leading benchmarks of performance, efficiency, and quality. You will collaborate closely with architects, software engineers, and hardware teams across NIC, HCA, switches, CPUs, and GPUs in a fast-paced and highly technical environment. This is an outstanding opportunity to join a highly skilled team and contribute significantly to groundbreaking technology! What you’ll be doing: Review architecture, build, and requirements for new networking features across Ethernet and InfiniBand portfolios Compose and build complex testbed topologies that emulate customer environments Implement, run and optimize integration test plans including functional, regression, and performance testing Identify, reproduce, and debug issues; work closely with R&D to drive root cause analysis and resolution Collaborate with automation teams Analyze and optimize network performance, latency, and efficiency Provide clear status updates, reports, and insights on system quality and performance What we need to see: B.Sc. in Computer Science, Electrical Engineering, or related field (or equivalent experience) 8&#43; years of experience in networking, system validation, or related engineering roles Strong hands-on experience with Linux-based systems Deep understanding of networking protocols (TCP/IP, UDP, Ethernet, VLANs, L2/L3) Experience with routing, switching, and modern data center network architectures<

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Summary Micron's Firmware & Product Test (FPT) team is hiring a Principal Test Development Engineer to lead front-end firmware validation for enterprise SSDs. In this role, you'll own verification strategy for NVMe front-end features, drive automation framework development, and serve as a technical authority for failure analysis and debug methodologies. You'll leverage AI-enabled tools and workflows to accelerate validation efficiency. You'll mentor engineers, define test coverage standards, and collaborate with firmware architects to influence testability decisions. The FPT team builds verification plans in Python, enforces NVMe and security protocol compliance, and executes white-box, grey-box, and black-box testing across simulation, FPGA, and prototype hardware environments. Responsibilities Lead design and execution of firmware verification strategies for NVMe front-end features (SMART, Trim, Get Log Page, OCP, Identify, Namespace Management) across multiple product lines. Own end-to-end test development lifecycle — from spec analysis and test planning through automation, execution, and coverage closure. Drive root-cause analysis for critical field and regression failures; establish systematic debug methodologies using coyote logs, protocol analyzers, and firmware traces. Architect and maintain scalable test automation frameworks that become organizational standards for firmware quality. Lead failure analysis efforts, correla

About the Team DoorDash Labs is an independent team within DoorDash. We explore robotics and automation to transform last mile logistics in the long term. If you have a passion for applying robotics solutions in a service used by millions of people, then we want to talk to you! About the Role We are hiring a Software Integration Engineer for our Platform Integration team. This is a critical role with impact across the robot lifecycle, from manufacturing to daily operation. The Platform Integration team owns making sure the robot works as one cohesive system. The focus is on the interfaces between subsystems; this role in particular is focused on the software side handling interaction between: OS & software stack; firmware; networking; timing; and calibration. In this role, you will work cross functionally with our electrical, hardware, firmware, and autonomy engineers to support new functionality both in both hardware and software. This includes creating provisioning tools, functional tests, and supporting integration into the autonomy software stack. You will report to the Autonomy Platform Lead on our Autonomy Platform Team at DoorDash Labs. We expect this role to be hybrid with some time in-office and some time remote. You’re excited about this opportunity because you will… Play an integral role on a small and focused team. Lead system-level debug when an issue crosses subsystem boundaries or no single team can isolate it. Support early integration of new sensor and software component designs by identifying interface requirements, risks, dependencies and required checks. Design and maintain integration tests, test setups, and procedures to ensure subsystems, once combined, satisfy requirements and design intent. Build and maintain the mission-readiness checks used before manufacturing signoff, validation, field testing, or mission use for different robot platforms. Create the tools, checks, and debug guidance that Manufacturing Integration, Validation,

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Join the front-end fabrics team and help shape the next generation of enterprise hardware platforms and software-defined data-center infrastructure. You will work at the intersection of hardware, operating systems, storage, networking, and distributed systems—solving complex problems that directly influence how customers deploy, operate, and scale their environments. This is an opportunity to own meaningful work across the full platform lifecycle: from early hardware bring-up and system validation through manufacturing release, customer deployment, upgrades, and fleet-level reliability. You will partner closely with hardware engineers, system architects, OS developers, and customers to turn ambitious platform requirements into robust, supportable products. WHAT YOU'LL DO Drive differentiated value from new hardware platforms by shaping architecture and design requirements that improve performance, scalability, and fleet-level efficiency—from early bring-up through manufacturing release, deployment, upgrades, and operations. Design, implement, debug, and deliver user-space software in C and C++ across storage protocols, networking, and data-center architectures. Develop and improve remote server-management capabilities using industry standards such as Redfish. Design and enhance Reliability, Availability, and Serviceability (RAS) features that make platforms easier to operate, diagnose, recover, and maintain at sca

What we’re doing isn’t easy, but nothing worth doing ever is. Diligent builds helpful robots that work safely and autonomously in real world environments. We move quickly, solve messy problems, and care deeply about reliability at scale. We’re hiring a Manufacturing Reliability Engineer to own production test for our robots at our contract manufacturer: you’ll design and run robust end-to-end test protocols, provision fleets of robots for production, and own the KPIs that define production quality. This role is based in Austin, TX. However, the position will require 50% travel to the Milwaukee, WI area and requires close collaboration across software, hardware, operations, and product engineering teams. Key Responsibilities End-to-end test process ownership. Create, validate, and maintain production test protocols and gating criteria from incoming inspection through final test and shipment. Provisioning of bots. Design and operate provisioning flows (imaging, firmware deployment, configuration, validation) and the tooling/fixtures needed to provision and handoff robots for production. KPIs and continuous improvement. Own key production metrics — First Pass Yield (FPY), cycle time, and test coverage — and drive continuous improvements to meet throughput and quality targets. Test automation & infrastructure. Architect, implement, and maintain automated test frameworks, harnesses, and test rigs used at the CM site. Ensure tests are stable, fast, and provide actionable failure data. Cross-functional escalation & RCA. Lead root-cause analysis for field and production failures; coordinate corrective actions with design, firmware, and CM engineering to close quality loops. On-site production leadership. Be the onsite technical authority at the contract manufacturer: train operators, debug failures on the line, and continuously refine processes with CM partners. What Success Looks Like Improved FPY and reduced rework rates across production builds. Reduced per