Hardware Debug And Validation Engineer Jobs

Senior-Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debu

Staff -Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debu

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Summary The role is responsible for end‑to‑end performance and power maturity of assigned Data Center SSD programs. The candidate owns execution quality, technical depth, and cross‑functional alignment to ensure performance and power targets are met with high confidence from early bring‑up through customer qualification. The role combines strong technical execution , data‑driven decision making , and program‑level leadership across firmware, architecture and platforms. Key Responsibilities Program Ownership & Execution Own end‑to‑end performance and power readiness for assigned programs, from early FW maturity through customer qualification. Ensure the delivery of high‑quality performance and power data aligned with program goals. Drive Program Status Updates for performance and power to Product Development team and other stakeholders. Technical Depth & Debug Perform in‑depth performance analysis and root‑cause debug , developing strong understanding of firmware behaviors, state machines, and hardware interactions. Identify performance risks early and work with FW, Arch, and System teams to drive mitigations. Represent pe

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Summary The role is responsible for end‑to‑end performance and power maturity of assigned Data Center SSD programs. The candidate owns execution quality, technical depth, and cross‑functional alignment to ensure performance and power targets are met with high confidence from early bring‑up through customer qualification. The role combines strong technical execution , data‑driven decision making , and program‑level leadership across firmware, architecture and platforms. Key Responsibilities Program Ownership & Execution Own end‑to‑end performance and power readiness for assigned programs, from early FW maturity through customer qualification. Ensure the delivery of high‑quality performance and power data aligned with program goals. Drive Program Status Updates for performance and power to Product Development team and other stakeholders. Technical Depth & Debug Perform in‑depth performance analysis and root‑cause debug , developing strong understanding of firmware behaviors, state machines, and hardware interactions. Identify performance risks early and work with FW, Arch, and System teams to drive mitigations. Repre

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Join Tenstorrent’s AI Models team and work at the layer most ML engineers never see: bringing advanced models to life on custom AI hardware. You’ll own real workloads end‑to‑end including porting, tuning, and validating LLMs and vision models on our accelerator, and chasing down every last millisecond and percentage point of accuracy. This role is for people who love the craft of ML engineering and want their work to matter at silicon scale, not just behind another API. This role is hybrid , based in Cyprus. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Bring up, run, and debug modern ML models (e.g., transformers) using PyTorch or TensorFlow. Analyze model behavior and performance, and identify bottlenecks across the stack. Improve efficiency, correctness, and scalability of model execution in real systems. Work closely with compiler, kernel, and hardware teams to drive performance and system-level improvements. Help translate state-of-the-art model architectures into production-grade, high-performance deployments. What We Need Strong experience building and working with ML models in PyTorch or TensorFlow. Strong understanding of mod

About Hark Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory. We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world. To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems. About the Role We’re looking for an experienced Audio Firmware Engineer to develop and optimize embedded audio solutions on Hark’s next-gen AI device. This role spans audio system bring-up, DSP algorithms development, integration and optimization, and deployment of advanced audio/AI features for consumer devices. The ideal candidate should be comfortable developing, integrating, debugging, tuning, and validating audio algorithms on an embedded production platform. Responsibilities Bring up audio processing stack on new hardware, drive implementation and integrations of audio processing pipeline Debug complex audio issues end-to-end using platform logs, working from kernel and DSP traces up through application-level symptoms Partner with the AI team to support audio-driven inference workloads (wake word, ASR, speech enhancement) within latency, power, and memory budgets Collaborate with hardware, acoustics, and product teams from prototype through production to ship audio that feels effortless to users Requirements 5+ years of professional firmware or embedded audio development, ideally on consumer products that have shipped at scale Experience with core Audio DSP algorithms and their implementations, including AEC, Beamforming, NR, AGC, VAD, DoA e

Who We Are Verkada is transforming how organizations protect their people and places with an integrated, privacy-sensitive AI-powered platform that includes solutions for video security, access control, air quality sensors, alarms, intercoms, and visitor management. We’ve got serious momentum in the market: more than 30,000 customers (including 100+ of the Fortune 500), a $5.8B valuation , more than $1 billion in annualized bookings, and backing from CapitalG, Sequoia Capital, General Catalyst, Felicis Ventures, Next47 and more. Physical AI is one of the most consequential technology shifts of our time, and Verkada is at the center of it. You can look at all kinds of communities to see our platform’s impact in the world. It's the retailer that uses our agentic AI to deter theft before it happens. The warehouse that uses AI-powered alerts to make sure its team is protected on the floor with proper PPE. The school that’s alerted to a threat in real-time and triggers a lockdown in seconds, not minutes. We’re rapidly scaling this impact: today, more than 2 million Verkada devices are deployed across 170+ countries. About the Role As a Hardware Engineering Intern at Verkada, you’ll contribute to the design and development of new cameras, access control systems, sensors, and other enterprise IoT products. Verkada’s Hardware Engineers own all aspects of the electrical design from prototype through to mass production. You’ll make a big impact — your designs will be a part of future products that Verkada ships. This is a full-time internship, in-person role based in our San Mateo, CA office. What You'll Do Partner with experienced engineers to design, debug, and validate our hardware products. Design and execute experiments to test new circuit concepts. Schematic capture and layout for systems and/or test boards. Learn to work with our manufacturing partners to drive ongoing improvements to efficiency. What You Bring Pursuing a degree in Electrical Engineering or

About the Team OpenAI’s Infrastructure organization builds and evaluates the systems that power advanced AI workloads. We work closely with hardware, modeling, and architecture teams to ensure that new platforms deliver real-world performance aligned with workload needs. Our team focuses on understanding workload behavior across evolving hardware platforms—bridging the gap between theoretical capability and observed system performance. About the Role We are seeking a Workload Porting & Performance Engineer to evaluate new hardware platforms by porting benchmarks and real-world workloads, analyzing performance, and identifying system bottlenecks. In this role, you will bring up workloads on new systems, characterize performance behavior, and adapt workloads to better utilize hardware capabilities. You will play a critical role in validating new platforms and ensuring that performance aligns with expectations across compute, memory, and networking subsystems. This role requires strong hands-on experience with performance analysis, workload optimization, and system-level debugging across hardware and software boundaries. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance. Key Responsibilities Port and enable benchmarks and real-world workloads on new hardware platforms. Evaluate system performance across compute, memory, storage, and networking subsystems. Identify and analyze performance bottlenecks and inefficiencies. Adapt and optimize workloads to better utilize hardware capabilities. Develop and run performance experiments and profiling workflows. Compare expected vs. observed performance and provide feedback to: hardware architecture teams performance modeling teams system and software engineers. Debug issues across the stack, including software, runtime, and hardware interactions. Provide actionable insights to guide platform readiness and deployment decisions. Qualifications E

Who We Are Verkada is transforming how organizations protect their people and places with an integrated, privacy-sensitive AI-powered platform that includes solutions for video security, access control, air quality sensors, alarms, intercoms, and visitor management. We’ve got serious momentum in the market: more than 30,000 customers (including 100+ of the Fortune 500), a $5.8B valuation , more than $1 billion in annualized bookings, and backing from CapitalG, Sequoia Capital, General Catalyst, Felicis Ventures, Next47 and more. Physical AI is one of the most consequential technology shifts of our time, and Verkada is at the center of it. You can look at all kinds of communities to see our platform’s impact in the world. It's the retailer that uses our agentic AI to deter theft before it happens. The warehouse that uses AI-powered alerts to make sure its team is protected on the floor with proper PPE. The school that’s alerted to a threat in real-time and triggers a lockdown in seconds, not minutes. We’re rapidly scaling this impact: today, more than 2 million Verkada devices are deployed across 170+ countries. About the Role We're focused on hiring embedded software engineers that understand not only the lower-level systems, but also how everything integrates together from the hardware to the UI. You’ll be working closely on one side with our hardware vendors and ME/EE people, and on the other side with server and UI engineers, industrial designers, and our operations team. If you’re looking for a fast-paced environment where your work is regularly shipping to customers and improving people’s safety, this is the place for you! What You'll Do Develop features for Linux embedded platforms - access control, intercoms, alarms Bring up and integrate the full stack: build system, kernel, drivers and userspace on real hardware Develop userspace applications Debug across the stack Define architecture and design new features Build prototypes and proofs of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an Hardware Emulation Architect on the HBM architecture team you will be responsible for architecting, enabling, and deploying hardware emulation capabilities for next generation HBM products. You will work with design, verification, firmware, and system teams to determine emulation needs and opportunities. You will drive the development of hardware emulation ecosystem including procurement of hardware emulation platforms, creation of emulation testbenches and transactors, and development of emulation friendly verification IP. You will be responsible for proactively developing emulation capabilities to meet the needs of current and future products. You will also lead the effort to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Responsibilities will include, but are not limited to: Develop and maintain hardware emulation environments for complex SoCs and subsystems. Compile, configure, and debug large-scale RTL designs on emulation platforms (e.g., Palladium, Veloce, Zebu). Support pre-silicon validation, firmware bring-up, and early software development using emulation. Debug functional, performance, and connectivity issues across RTL, firmware, and system layers. Work closely with design, verification, firmware, and architecture teams to enable rapid debug and issue resolution. Create emulation testbenches, transactors, and models for system-level use cases. Enable hybrid validation flows (simulation + emulation

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Join forces with us on our mission to build a better IT industry. We are currently looking for a highly skilled Android BSP Engineer to our team in Stockholm or Malmö, Sweden. Please note that applicants must live in Sweden and hold a valid work permit at the time of application to be considered for this role. Responsibilities: Bring up Android on new custom hardware, from initial kernel boot through a fully functioning Android system Develop and customize the Android platform and board support package Configure and maintain the Linux kernel, device tree, boot configuration, and Android device configuration Integrate the Android software stack with custom hardware Integrate, port, develop, and maintain drivers and interfaces for RFID readers, sensors, and other peripherals Develop and integrate Android HALs, native services, system services, and application-facing APIs Configure Android init services, device permissions, SELinux policies, and VINTF manifests Diagnose problems across the bootloader, kernel, drivers, HALs, Android framework, and applications Debug hardware and software integration issues using logs, traces, test equipment, and hardware-debugging tools Optimize boot time, system performance, stability, power consumption, and reliability Build, configure, flash, and maintain Android system images Support system valid

About the job Build the test systems that prove advanced AI hardware is ready before it reaches production. As a Test Development Engineer, you will create and maintain test systems for Graphcore’s electronic hardware platforms. Your work will support preproduction test solutions across system and board-level products. You will define test methods, specify equipment and automate systems for complex hardware. This includes high-speed serial links, high-current power supplies, slower protocols and low-level PCBA debug. This role sits close to real engineering problems. You will build deep product knowledge, improve test coverage and help transfer robust solutions into production. The team and culture You will join the Hardware Test team, embedded within Graphcore’s wider Hardware Engineering group. The team works closely with SI, mechanical, layout, package, silicon, firmware and production teams. Work moves through practical test design, lab debug, automation and clear data. You will be trusted to take ownership and develop solutions that meet real hardware needs. The team values proactive communication across Graphcore and third-party support teams. Decisions are shaped by evidence, standards knowledge and the quality of the test data. What we’re looking for · Experience developing and automating test systems for complex electronic systems · Knowledge of Ethernet and/or PCIe testing, including high-speed hardware debug · Fluency in test scripting languages, including Python and LabView · Ability to plan test work, improve coverage and communicate progress clearly · Hands-on experience with lab equipment such as oscilloscopes, BERTs and VNAs · Strong ownership, teamwork and communication skills across technical teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how your background makes you a strong candidate. Benef

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is seeking a highly skilled Device Driver Engineer to design and implement high-performance driver stack for our cutting-edge AI accelerator hardware. In this role, you will work closely with hardware, firmware, and AI software teams to develop low-latency, high-bandwidth communication between the host system and AI accelerator. Responsibilities Develop, optimize, and maintain Linux/Windows PCIe device drivers for AI accelerators. Implement low-level hardware interactions, DMA, memory management, and interrupt handling. Work on driver optimizations to reduce latency and improve throughput for AI workloads. Debug and troubleshoot PCIe protocol, kernel panics, crashes, and performance bottlenecks. Collaborate with hardware, firmware, and AI software teams to define driver interfaces. Ensure compliance with PCIe standards (Gen4/Gen5), SR-IOV, BAR memory mapping, and IOMMU. Support virtualization (VFIO, SR-IOV, DPUs) and containerized environments (Kubernetes, Docker, etc.). Develop tools for profiling, debugging, and monitoring driver performance. Contribute to open-source kernel modules if applicable. Qualifications Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field. 3+ years of experience in device driver development for Linux and/or Windows. Strong experience with PCIe-based hardware, including BAR

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a C++ Machine Learning Engineer on the AI Models team at Tenstorrent, you’ll work on the training framework behind our most advanced models. You’ll write high-performance C++ code, shape how new layers and operators are implemented, and help models scale across our custom silicon. If you enjoy building the guts of ML systems and seeing them run fast, this role is for you. This role is hybrid, based out of Warsaw or Gdansk, Poland. We also consider remote candidates within Poland on a case-by-case status. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Strong in C++ and low-level systems programming, especially in performance-critical code. Comfortable thinking in tensors, memory layout, and compiler graphs. Familiar with PyTorch and curious about how frameworks map to hardware. A builder who enjoys solving technical puzzles and digging into the details. What We Need Extend and optimize our ML training framework with new ops, layers, and training features. Debug and tune model performance on Tenstorrent chips. Work with compiler and kernel teams to make sure models compile and run as expected. Support integration of real-world models

NK Securities Research is a leading financial firm that leverages cutting edge technology and sophisticated algorithms to trade the financial markets. Founded in 2011, we have gained invaluable experience in the field of High Frequency Trading across different asset classes. With a focus on innovation, entrepreneurship, and collaboration, we aim to foster a dynamic work environment that reflects a startup culture. Role Overview As an FPGA Developer, you will design, implement, and rigorously test RTL (Register-Transfer Level) designs to power our high-frequency trading strategies. Your contributions will play a pivotal role in reducing system latency and enhancing performance, directly impacting trading outcomes. Key Responsibilities Design and Implementation: Develop high-performance RTL designs using VHDL or Verilog for FPGA-based systems. Optimize hardware implementations for ultra-low latency and high throughput. Testing and Debugging: Perform thorough functional and timing testing of RTL designs, ensuring adherence to specifications. Debug and resolve issues using FPGA debugging tools such as SignalTap, ChipScope, or ModelSim. Collaboration and Documentation: Work closely with hardware and software teams to ensure seamless integration of FPGA solutions with the Software Trading Stack. Maintain clear and comprehensive documentation of designs, test cases, results and benchmarks Qualifications Technical Skills: RTL Development: Strong fundamentals in digital logic design, Boolean algebra, FSMs and synchronous design. Proficiency in VHDL or Verilog/SystemVerilog, with a strong focus on efficient and optimized designs. FPGA Tools: Hands-on experience with industry-standard tools such as Xilinx Vivado. Testing and Verification: Expertise in writing testbenches and conducting simulation-based verification. Familiarity with static timing analysis and achieving timing closure. Familiar with CocoTB or any similar testing setup. Debugging: Proficiency in GHDL synthesis a