Hardware Debug And Validation Engineer Jobs

What we’re doing isn’t easy, but nothing worth doing ever is. Diligent builds helpful robots that work safely and autonomously in real world environments. We move quickly, solve messy problems, and care deeply about reliability at scale. We’re hiring a Manufacturing Reliability Engineer to own production test for our robots at our contract manufacturer: you’ll design and run robust end-to-end test protocols, provision fleets of robots for production, and own the KPIs that define production quality. This role is based in the Milwaukee, WI area and requires close collaboration across software, hardware, operations, and product engineering teams. We welcome applicants from outside Milwaukee who are willing to relocate. Relocation assistance/bonus will be a part of compensation package. Key Responsibilities End-to-end test process ownership. Create, validate, and maintain production test protocols and gating criteria from incoming inspection through final test and shipment. Provisioning of bots. Design and operate provisioning flows (imaging, firmware deployment, configuration, validation) and the tooling/fixtures needed to provision and handoff robots for production. KPIs and continuous improvement. Own key production metrics — First Pass Yield (FPY), cycle time, and test coverage — and drive continuous improvements to meet throughput and quality targets. Test automation & infrastructure. Architect, implement, and maintain automated test frameworks, harnesses, and test rigs used at the CM site. Ensure tests are stable, fast, and provide actionable failure data. Cross-functional escalation & RCA. Lead root-cause analysis for field and production failures; coordinate corrective actions with design, firmware, and CM engineering to close quality loops. On-site production leadership. Be the onsite technical authority at the contract manufacturer: train operators, debug failures on the line, and continuously refine processes with CM partners. What Success Looks

itD is seeking a DFT (Design For Test) Lead to drive the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle, ensuring highly testable, manufacturable, and reliable ASIC designs. The ideal candidate will bring deep expertise in ASIC DFT methodologies, post-silicon validation, and test architecture development, with a proven track record of delivering production-ready silicon through cross-functional collaboration. Location: Hybrid in Carlsbad, CA or Allentown, PA , or U.S. Remote . Candidates must be available to work Pacific Time business hours (9:00 AM–5:00 PM PST). Duration: 14 months We provide comprehensive medical benefits, a 401k plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship. Responsibilities: Lead the implementation of hardware Design-for-Test (DFT) features, including scan, memory BIST (MBIST), BISR, boundary scan, and DFT simulation setup and debugging. Develop innovative DFT IP in collaboration with cross-functional engineering teams and integrate testability features into full-chip RTL designs. Drive reusable DFT and debug methodologies for next-generation silicon devices, including bare die and stacked die architectures. Perform post-silicon debugging, root cause analysis, and production qualification activities to improve silicon yield, reliability, and manufacturability. Collaborate with physical design, validation, and hardware engineering teams throughout the complete silicon product lifecycle. Design, validate, and release ATPG patterns while supporting manufacturing test readiness and production ramp. Develop technical solutions and resolve complex DFT challenges with minimal supervision while providing technical leadership to the broader engineering team. Internal Responsibilities: Attend regular internal practice community meetings. Collaborate with your itD practice team on ind

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are seeking a highly skilled and experienced System Debug Lead Engineer to join our team. This individual will play a critical role in root cause analysis and resolution of complex issues across our server and data center platforms, involving electrical, mechanical, thermal, and firmware components. The ideal candidate brings a multidisciplinary approach to system-level problem-solving and thrives in a dynamic, collaborative environment. What you’ll be doing: Lead cross-functional debug of critical system-level issues across hardware (electrical, mechanical, thermal) and firmware domains Perform hands-on root cause analysis of failures observed during system validation, production, or in-field operation Collaborate with electrical engineers, mechanical engineers, thermal engineers, firmware developers, and manufacturing teams to develop and validate fixes Develop and implement detailed tests and experiments to identify and recreate intricate issues Develop tools, scripts, and automation to accelerate debug workflows Provide technical guidance and mentoring to cross-functional teams Document debug procedures, findings, and mitigation pla

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We're seeking a Security Engineer to join our First-Party Hardware team. In this role, you will own the end-to-end security foundation for OpenAI's first-party AI hardware systems, working across hardware security, embedded security, system security, and practical deployment at data center scale. You will partner with silicon, hardware, firmware, infrastructure, manufacturing, operations, and security teams to define and deliver system-level device trust. This includes boot integrity, device identity, provisioning, attestation, management-plane security, storage encryption, debug controls, firmware update and recovery, RMA, and decommissioning. You will be accountable for turning threat models into requirements, requirements into implementation, and implementation into validation evidence that can support launch decisions. Location: San Francisco, CA (Hybrid: 3 days/week onsite) Relocation assistance available. In this role, you will: Own security requirements, threat models, validation strategy, and launch-readiness evidence for first-party hardware platforms from early design through production deployment. Design and review secure boot, measured boot, roots of trust, platform firmware resilience, firmware signing, recovery, and anti-rollback strategies across heterogeneous devices. Own device identity, provisioning, enrollment, attestation, certificate lifecycle, and key-management requirements across manufacturing and data center bring-up. Harden management

Senior: PLN 260,400 - 352,200 Staff PLN 350,700 - 474,400 Subject to alignment to the responsibilities and duties of the role - we currently have multiple positions available at both Senior and Staff level. About the job Build the quality foundations for Kubernetes systems that power next-generation AI compute. As a Staff QA Engineer, you will validate the workload management stack for new AI accelerator hardware. You will help ensure our Kubernetes integrations are robust, scalable and ready for production. Your work will shape how accelerators are scheduled, orchestrated and used across distributed environments. You will test the systems that make complex AI compute infrastructure reliable for real users. You will design automated test suites, build system and integration tests, and improve CI/CD quality practices. You will also debug issues across Kubernetes, infrastructure and applications. This role is for someone who wants to raise engineering quality across a deeply technical platform. The team and culture You will join the Workload Management team, working closely with software engineers and infrastructure specialists. The work is hands-on, systems-focused and driven by clear technical ownership. Quality is built early here, not checked at the end. You will influence test strategy, validation plans and automation practices across the development lifecycle. The team moves through open technical discussion and evidence-based decisions. You will mentor others, speak up on risk and help turn complex systems into dependable products. What we’re looking for Strong Python programming experience, with a focus on automation and test engineering Hands-on experience with Robot Framework or similar automation frameworks Experience testing cloud-native, containerised or distributed systems Strong Linux understanding and confidence debugging across multiple system layers Experience with CI/CD systems such as GitLab CI or GitHub Actions Ability to define quality standards,

About the job Own the test strategy that proves Graphcore’s next generation drivers are production-ready. As a Staff System Software Engineer, you will shape how Graphcore validates complex device drivers and platform tools. You will bring technical depth across Linux kernels, drivers and systems software. Your work will help raise the quality bar for products that support the next generation of AI compute. You will influence design decisions, guide test infrastructure and drive reliability across the stack. You will design, build, execute and report tests across component, system and acceptance levels. You will debug difficult issues using hardware and software tools, simulators and emulators. This is a hands-on technical leadership role with broad reach. You will help teams move quickly while protecting production quality. The team and culture The Drivers QA team verifies low-level kernel drivers, user-space libraries and platform tools. Work spans component tests, user acceptance and full system validation. You will work directly with driver developers, hardware, firmware, ML stack, Kubernetes and cloud management teams. Decisions are made close to the technical detail, with engineers expected to speak up and own outcomes. The team values engineers who think big, act fast and take responsibility. You will mentor others, raise standards and turn hard system problems into lasting improvements. What we're looking for · Deep experience validating Linux kernels, device drivers or similar systems software · Strong C++ and Python test development skills · Experience with CI/CD, build tools and modern automated testing practices · Ability to debug complex issues across hardware, firmware, drivers and upper software layers · Proven ownership of technical work, priorities and delivery in an agile engineering setting · Clear communication skills, including the ability to document and explain complex technical concepts While we have outlined a set of requirements, we value t

About the job Own the test strategy that proves Graphcore’s next generation drivers are production-ready. As a Staff System Software Engineer, you will shape how Graphcore validates complex device drivers and platform tools. You will bring technical depth across Linux kernels, drivers and systems software. Your work will help raise the quality bar for products that support the next generation of AI compute. You will influence design decisions, guide test infrastructure and drive reliability across the stack. You will design, build, execute and report tests across component, system and acceptance levels. You will debug difficult issues using hardware and software tools, simulators and emulators. This is a hands-on technical leadership role with broad reach. You will help teams move quickly while protecting production quality. The team and culture The Drivers QA team verifies low-level kernel drivers, user-space libraries and platform tools. Work spans component tests, user acceptance and full system validation. You will work directly with driver developers, hardware, firmware, ML stack, Kubernetes and cloud management teams. Decisions are made close to the technical detail, with engineers expected to speak up and own outcomes. The team values engineers who think big, act fast and take responsibility. You will mentor others, raise standards and turn hard system problems into lasting improvements. What we're looking for · Deep experience validating Linux kernels, device drivers or similar systems software · Strong C++ and Python test development skills · Experience with CI/CD, build tools and modern automated testing practices · Ability to debug complex issues across hardware, firmware, drivers and upper software layers · Proven ownership of technical work, priorities and delivery in an agile engineering setting · Clear communication skills, including the ability to document and explain complex technical concepts While we have outlined a set of requirements, we value t

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Micron’s SSD Hardware Architecture organization, where we develop the technologies that power next-generation storage solutions. We work across architecture, silicon, firmware, and product engineering teams to deliver high-performance SSD controllers that meet demanding standards for quality, reliability, and innovation. As a Staff SSD Hardware PCIe Engineer, you will play a key role in bringing advanced SSD controller technologies to life. This position offers the opportunity to lead PCIe subsystem validation, debug complex system-level challenges, and influence future product capabilities while collaborating with highly skilled engineering teams across the organization. Responsibilities: Develop hardware and system specifications from architectural and product requirements Lead PCIe bring-up, characterization, debugging, validation, and compliance activities for SSD controller SoCs Partner with architecture, verification, firmware, product engineering, and external IP vendors to resolve issues and improve functionality Drive system-level validation methodologies, automation, and test development to improve coverage and efficiency Perform root-cause analysis and validate PCIe functionality across complex SSD use cases Minimum Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field, or equivalent experien

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Join Micron’s SSD Hardware Architecture organization, where we develop the technologies that power next-generation storage solutions. We work across architecture, silicon, firmware, and product engineering teams to deliver high-performance SSD controllers that meet demanding standards for quality, reliability, and innovation. As a Staff SSD Hardware PCIe Engineer, you will play a key role in bringing advanced SSD controller technologies to life. This position offers the opportunity to lead PCIe subsystem validation, debug complex system-level challenges, and influence future product capabilities while collaborating with highly skilled engineering teams across the organization. Responsibilities: Develop hardware and system specifications from architectural and product requirements Lead PCIe bring-up, characterization, debugging, validation, and compliance activities for SSD controller SoCs Par

About the Team OpenAI’s Hardware organization develops custom silicon and systems for advanced AI workloads. Our first-party accelerator team works across chip architecture, design, software, and systems to build the computing platforms that power frontier models. We are a small, dynamic team that values technical breadth, hands-on engineering, and creative approaches to building complex hardware. About the Role We’re looking for a SoC Engineer to help architect, design, and integrate OpenAI’s first-party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects our accelerator designs into complete, functional systems. This role combines architectural judgment with hands-on implementation. You’ll work closely with design, architecture, verification, and software teams throughout development, from defining subsystem requirements and integrating IP to pre-silicon validation, silicon bring-up, and post-silicon debug. You should enjoy stretching across domains, rolling up your sleeves, and doing the work needed to make a complex system function end to end. In this role, you will: Define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCI Express, Ethernet and die-to-die interfaces. Develop the microarchitecture and RTL design of subsystems supporting I/O and SoC functionality. Integrate Arm Cortex-M and Cortex-A processors, AXI/APB fabrics, and third-party controller IP, including the RTL and glue logic needed to connect these components. Develop reset and boot architectures, working with firmware and software teams to define sequencing, initialization, and survivability behavior. Incorporate debug, test, and security requirements into the SoC architecture and implementation, partnering with other silicon designers to make the silicon observable, testable, and secure. Drive PCIe and other I/O integration, including controller and PHY interfaces, high-speed SerDes,

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation. To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website. About the Role GreenWave Radios is seeking a highly technical Staff RF System Test Engineer to develop, automate, and execute system-level validation of next-generation RF SoC platforms from early silicon bring-up through production release. You will be a hands-on contributor responsible for uncovering complex RF performance issues, building scalable test infrastructure, and generating the data that drives critical design decisions. As a member of the Systems Engineering Group in San Jose, CA, this role sits at the intersection of RF hardware, embedded software, and test automation. You will work directly with designers and developers to characterize radio performance, debug challenging system behaviors, and create robust automated test solutions that ensure compliance with global wireless standards. The ideal candidate combines deep RF measurement expertise with strong software development skills and enjoys solving difficult technical problems through rigorous experimentation and data-driven analysis. What You'll Do Des

Graphcore is a globally recognized leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and datacentre hardware that provide the specialized processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, we are working to enable Artificial Super Intelligence and ensure that its benefits are accessible to everyone. We are developing the next generation of AI compute, a large-scale system-on-chip (SoC) designed to power future high-performance AI systems. As the Director of Post Silicon Validation, you will be responsible for leading the Bristol team, enabling pre-production software to run reliably on new silicon quickly and efficiently, before showing that the silicon meets the highest standards of quality, reliability and functionality, ready for production deployment. Reporting to the Senior Director of Post Silicon Validation, you will manage, develop and grow the Post Silicon Validation team in Bristol, delivering post-silicon validation across the full AI SoC, working across silicon, firmware, and platform levels. The role requires a deep technical understanding, strong hands-on debug experience, and the ability to collaborate effectively with hardware, software, and systems engineering teams. Responsibilities Manage, develop and grow the Post Silicon Validation team in Bristol: The Post Silicon Validation team is relatively new, with a strong remit and growing quickly to help Graphcore bring up new silicon quickly and effectively. Play a significant role in the definition, planning and execution of chip bringup activities: Develop and refine the overall post-silicon validation approach for our AI SoCs, ensuring reliable and timely delivery of validated silicon, architectural correctness, feature r

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As an STPG PE System Engineer , you will support SSD products from product development and qualification through manufacturing ramp and high-volume production, with focus on product quality, manufacturing readiness, yield improvement, and technical issue resolution. This aligns with the established STPG Product Engineering mission of transitioning products from design through qualification and high-volume manufacturing. You will collaborate with cross-functional engineering teams including Product Engineering, Firmware, NAND, ASIC, Hardware, Test, Manufacturing, and Quality to deliver robust and manufacturable SSD products. Responsibilities Drive SSD product engineering execution including manufacturing test bring-up, product qualification, firmware/test validation, and production readiness . Analyze test yield, characterization data, test limits, and manufacturing performance to identify issues and drive continuous improvement. Perform system-level failure analysis and root-cause investigation , working across Firmware, NAND, ASIC, Hardware, and Manufacturing teams to resolve complex product issues. Develop and improve test, debug, data analytics, automation, and AI-enabled engineering solutions to improve

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is hiring an ATE Test Development Engineer who can build sophisticated, scalable test solutions on the Advantest V93000 platform using SmartTest 8, custom code, and low‑level tester APIs. This role is ideal for someone who enjoys writing clean, modular software that directly touches hardware, understands how measurements are supposed to work, and can drive experiments that isolate variables across silicon, instrumentation, and test methodology. You will own the development, debug, datalogging, and optimization of ATE test content for NPI and production, ensuring our devices are thoroughly characterized, efficiently tested, and ready for high‑volume manufacturing. This role is hybrid, b ased out of Austin,TX; Santa Clara,CA; or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 10+ years of experience in ATE test development, semiconductor test engineering, or post-silicon validation. You are proficient with Advantest V93000, SmartTest 8, tester APIs, C++ or Java, and Python automation. You understand ATE instrumentation, including DPS, PMU, RF/HSIO, timing sets, multisite execution, and tester-to-DUT

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is hiring a System-Level Test (SLT) Engineer to ensure our silicon behaves predictably when running real workloads in real systems. You’ll build the software and system infrastructure that enables validation tests to operate reliably in manufacturing, while applying structured debug to separate hardware issues from software, interface, and environmental effects. This role is ideal for someone who understands how tests are constructed and how silicon responds under stress—and who can turn that insight into scalable, production-ready solutions. Candidates will be assessed for the appropriate level during the interview process, and the offer level may differ from the level listed in this posting. This role is hybrid, based out of Austin,TX; Santa Clara,CA; or Fort Collins, CO . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 10+ years of experience in system-level test, embedded systems, software architecture, or hardware/software integration, with strong skills in C/C++, Python, or similar languages. You apply object-oriented design principles to build modular, maintainable, and extensible test frameworks