Hbm Process Engineer Jobs

HBM ENGINEERING SUPPORT TECHNICIAN — Taichung - AATT, Taiwan. Apply via Workday.

HBM Equipment Technician 輪班助理工程師 — Taichung - MTB, Taiwan. Apply via Workday.

HBM Hardware Emulation Architect — 2 Locations. Apply via Workday.

HBM 招募專區｜加入 MTB，站上 AI 與先進記憶體最前線 — Taichung - MTB, Taiwan. Apply via Workday.

HBM Customer Systems Validation Engineer — 2 Locations. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. HBM Core-Die Architecture & Circuit Design Engineer This role owns next‑generation HBM core‑die architecture and critical DRAM circuit design that directly impact bandwidth, power, area, thermal efficiency, and long‑term reliability. The engineer will drive architecture definition, circuit feasibility, and Architecture Reference Design (ARD) development across advanced 3D‑stacked HBM products. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Key Responsibilities Own HBM core‑die architecture including Bank/Bank‑Group organization, array partitioning, datapath, refresh, and reliability features Drive critical DRAM circuit design and timing closure for row, column, sensing, and datapath paths Develop and optimize architecture solutions for bandwidth, power, area, thermal, and reliability trade‑offs Define and validate refresh, row‑hammer mitigation, data‑retention, and power‑efficient operation schemes Lead architecture feasibility studies using transistor‑level simulation and physical implementa

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High Bandwidth Memory (HBM) organization develops industry-leading memory solutions that power artificial intelligence, high-performance computing, graphics, and data center applications. The team brings together experts across architecture, design, verification, physical design, product engineering, and validation to deliver advanced memory products that enable the world's most demanding computing workloads. As an HBM Design Development Technical Leadership (DDTL) Intern, you will support the planning, execution, and coordination of next-generation HBM product development programs. You will work closely with technical leaders and engineering teams to track project execution, manage risks, analyze program data, and improve engineering productivity through automation, analytics, and AI-enabled workflows. This role offers exposure to both the technical and leadership aspects of semiconductor product development. Responsibilities Support HBM product execution by tracking schedules, achievements, dependencies, technical risks, and design readiness throughout the development lifecycle. Collaborate with multi-functional engineering teams to monitor project status, coordinate deliverables, and support successful achievement completion. Develop dashboards, reports, data analytics solutions, and executive summaries to provide transparency into program health and key performance indicators. Create automation tools, workflow improvements, and AI-assisted solutions that improve engineering productivity, de

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Responsibilities Validation Execution Assist in executing Validation Runs on IQP/ETV materials under defined timelines, ensuring coverage completeness across MBIST and Native Mode flows. Support time-bound data crunching (log parsing, statistical summaries) and contribute to summary report preparation. Platform & Test Program Support Operate and debug programs on SM3/Cobra (MBIST) and Advantest V93K (Native) . Assist in hardware readiness: handler, socket, loadboard, and probe card setup. Technical Analysis & Simulation Validate high-speed I/O (>11 Gbps) and assist with eye diagram and signal integrity checks. Support Verilog simulation tasks (testbench execution, waveform review) to reproduce sightings and validate fixes. Data & Automation Develop basic scripts in Python for log parsing and data visualization. Maintain documentation in Confluence/Jira and version control in Git/Perforce. Debug & Collaboration Participate

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Responsibilities Yield Loss Accounted For Account for HBM NPI builds across PWF, Assembly, and test through defect breakdown and PFA submission to understand fail mode Work closely with PI to identify defect that is coming from their area to brainstorm for CIP Learn NPI processes, phase gates, and yield best practices Assist in maintaining yield dashboards and trackers. Support PI/PE/RDA in identifying and transforming processing data to account/ breakdown a yield loss Yield Deviation Control Analyze and report on yield deviation issue and trigger action from PI, PE or RDA Support block run and partial conversion build yield analysis to early detect any impact on yield Work closely with PCS team to identify SPC or FDC charts to put into YLR dashboard for shift left monitoring Yield Improvement Opportunities Brainstorm with staff from other departments to brainstorm for improvement opportunities to propose to PI Utilize software tool like Auto-diagnostics to find yield improvement opportunities Integrating Artificial Intelligence Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgement and complying with organizational standards and legal requirements Contributes to a culture of continuous improvement by identifying, testing, and sha

Sr HBM Design Architect, PhD NCG — 2 Locations. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Within Micron’s Heterogeneous Integration Group (HIG), we are developing advanced High Bandwidth Memory (HBM) solutions that enable the next generation of AI, high-performance computing, and data-centric applications. Our team collaborates across design, product, manufacturing, and ecosystem partners to deliver innovative memory technologies with exceptional quality and execution excellence. The HBM Tapeout and Release Technical Lead plays a critical role in ensuring successful design releases into Micron manufacturing. In this role, you will drive tapeout execution, release readiness, and design governance across complex HBM programs, partnering with design, integration, verification, and product teams to deliver high-quality designs on schedule. Responsibilities: Lead tapeout execution and release coordination for HBM builds, managing schedules, DBR achievements, and release readiness Drive preparation, review, and completion of tapeout collateral, including TOAST, RCDB, TWIT, and related release documentation Coordinate signoff readiness across timing, power, physical verification, integration, and other release-critical activities Ensure database quality, completeness, traceability, and signoff evidence are in place prior to tapeout Manage release risks, waivers, open items, and governance processes while maintaining strong r

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Responsibilities Validation Execution Assist in executing Validation Runs on IQP/ETV materials under defined timelines, ensuring coverage completeness across MBIST and Native Mode flows. Support time-bound data crunching (log parsing, statistical summaries) and contribute to summary report preparation. Platform & Test Program Support Operate and debug programs on SM3/Cobra (MBIST) and Advantest V93K (Native) . Assist in hardware readiness: handler, socket, loadboard, and probe card setup. Technical Analysis & Simulation Validate high-speed I/O (>11 Gbps) and assist with eye diagram and signal integrity checks. Support Verilog simulation tasks (testbench execution, waveform review) to reproduce sightings and validate fixes. Data & Automation Develop basic scripts in Python for log parsing and data visualization. Maintain documentation in Confluence/Jira and version control in Git/Perforce. Debug & Collaboration Participate in root cause analysis sessions and assis

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has been at the forefront of innovation, delivering the world’s most advanced memory and semiconductor technologies. Our distributed team of engineers, scientists, and visionaries is developing groundbreaking solutions that redefine how the world uses information to enrich life for all. We are seeking a Layout Design Engineering Manager to join Micron’s High Bandwidth Memory (HBM) organization in Guadalajara, Mexico. In this leadership role, you will guide a distributed team focused on developing complex analog, mixed‑signal, and custom layouts powering next‑generation AI and high‑performance computing solutions. Responsibilities Manage a team responsible for crafting and developing critical layouts for analog circuits, mixed-signal components, and custom blocks, including support for full-chip-level integration. Oversee layout verification activities, including LVS, DRC, Antenna checks, documentation, and quality reviews. Ensure timely and high‑quality delivery of block‑level layouts that meet all project requirements. Coordinate planning, area/time estimation, scheduling, task delegation, and execution for multiple concurrent projects. Mentor and guide layout engineers of all levels. Perform detailed reviews of sub‑block‑level layouts. Collaborate with global engineering teams to drive successful project execution and alignment across Micron’s worldwide footprint. </

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology has delivered world‑leading memory and semiconductor solutions. As an HBM Memory Design Engineer on the HBM Architecture Team, you will design, simulate, optimize, and floorplan advanced DRAM circuits for next‑generation High Bandwidth Memory products. You will work across digital, analog, and mixed-signal domains to ensure functional correctness, performance, and power efficiency. Your role includes collaborating with globally distributed teams developing modern HBM solutions for AI and ML applications. Responsibilities • Design, simulate, and optimize DRAM memory arrays, data paths, ECC, command/control logic, and high‑speed interface circuits • Evaluate block‑level and full‑chip functionality and propose solutions to ensure functional correctness • Analyze timing, area, power, and complexity trade‑offs in high‑speed DRAM and mixed‑signal designs • Perform pathfinding and feasibility studies for new architectures and future HBM products • Contribute to the design, layout, and optimization of memory, logic, and analog circuits • Support large‑scale verification, debug, and silicon validation activities • Collaborate across multi-functional teams involved in TSV‑based 3D stacking and vertical integration • Participate in design reviews and drive continuous improvement of design methodologies Minimum Qualifications • BSEE with 7&#43; years or MSEE with 5&#43; years of relevant engineering experience • Strong knowledge of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines! As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams. Responsibilities: Define and implement end-to-end DFT architectures for HBM base die and DRAM die Develop DFT strategies for stacked-die, cube-level, and system-level test flows Architect test access mechanisms supporting wafer probe through final test Enable silicon observability for yield learning, debug, and failure analysis Collaborate across design, verification, layout, test, and manufacturing teams Minimum Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts Experience with wafer probe and fin