High Speed Hardware Developer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Micron’s High Bandwidth Memory (HBM) Design Verification team is responsible for ensuring the functionality, performance, and quality of next‑generation memory products that enable advanced computing applications. As a Senior Design Verification Engineer, you will collaborate closely with design, architecture, and product engineering teams to verify complex, high‑density DRAM circuits and deliver robust, production‑ready designs. This role combines deep technical verification expertise with cross‑functional collaboration in a global environment. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high speed designs, sophisticated functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies. You will be responsible to evaluate the functionality and performance of the Full-chip and block-level circuit designs using different verification tools, techniques, and strategies. In addition, you will also n

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Staff Verification Architect and shape modular, scalable verification solutions for next-generation HBM DRAM products across multiple customer platforms! You will be part of a highly multi-functional team of technical domain experts. You will collaborate closely with Design Engineering, Product Engineering, Business Units, and external customer teams to ensure our future HBM roadmap is successful. You will apply your thorough understanding of testbench architecture, custom and SoC verification methodologies, and 2.5D & 3D package integration to analyze bottlenecks and propose innovative solutions targeting scalability, quality, and verification cycle time. Responsibilities: Deliver high-quality, on-time verification plans and architecture collateral across IP-level and SoC-level verification, and develop turnkey solutions for future designs based on look-ahead information from customers and the architecture team Drive co-verification through direct customer interactions, and mentor early-career engineers to strengthen team capability and tech

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) develops next-generation High Bandwidth Memory (HBM) solutions for AI, machine learning, and high-performance computing applications. We are seeking an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products. This role focuses on PHY IO architecture, timing methodology, analog calibration schemes, and silicon learning frameworks that enable industry-leading bandwidth, power efficiency, and robustness. The successful candidate will collaborate across Design, Product Engineering, Modeling, Verification, Packaging, and System Architecture teams to define architectural requirements, drive technology innovation, and ensure successful translation from concept to silicon. As a technical leader, you will influence future HBM roadmap decisions, develop engineering methodologies, and mentor design teams on architectural principles, calibration strategies, and best practices for high-speed IO design. Key Responsibilities Define and drive next-generation HBM PHY and IO architecture , balancing performance, power, area, reliability, and manufacturability requirements. Architect high-performance transmit and receive paths , including clocking, signaling, equalization, timing alignment, and interface optimization. Define and optimize analog calibration architectures , including impedance calibration, reference v

This is Adyen Adyen provides payments, data, and financial products in a single solution for customers like Meta, Uber, H&M, and Microsoft - making us the financial technology platform of choice. At Adyen, everything we do is engineered for ambition. For our teams, we create an environment with opportunities for our people to succeed, backed by the culture and support to ensure they are enabled to truly own their careers. We are motivated individuals who tackle unique technical challenges at scale and solve them as a team. Together, we deliver innovative and ethical solutions that help businesses achieve their ambitions faster. Senior Product Manager - Data, Machine Learning and GenAI Platform 20 years of payments data is a powerful asset. But only combined with the proper platform and solid processes, it can release its full potential. That’s why the Big Data, Machine Learning and GenAI platforms, within the Application Intelligence portfolio, are key for Adyen’s success. Platform Engineering builds Adyen’s internal developer platform as a Product, enabling our internal developers to autonomously build, run and maintain secure, scalable, and reliable applications with high speed and quality. Our data platform supports the creation and evolution of different data products ( e.g. Machine Learning models, GenAI apps, data pipeline, insights dashboards), impacting both merchants and key internal processes. The platform is currently serving 600+ active users including Data Engineers, Machine Learning Scientists, Applied AI Engineers or Data Analysts. All of them use data as their main asset, at the same time they all have different needs. As a Senior Product Manager, you will directly interact with this group to understand their user journeys and identify and prioritize opportunities for the platform to improve. Your goal is to bring the data developer experience (DevEx) to the next level, setting every user persona for success while keeping

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As Staff Engineer in Micron’s High Bandwidth Memory (HBM) Component Validation team, you will contribute as Subject Matter Expert (SME) and contribute to define new standards on validation development for advanced HBM products and ensure stable, scalable validation testing infrastructure with zero code-related escapes across MBIST, Native test modes and high speed memory validation. You own optimizing test flows, and lead technical problem solving for next generation HBM products. You’ll drive validation development deliverables and mentor junior engineers. Why Join Us You’ll gain hands-on experience with cutting-edge HBM technologies and validation platforms, working alongside global experts. This role offers opportunities to learn advanced validation techniques, drive and deliver product readiness, technology solutions and innovations, and grow into technical leadership roles. Responsibilities Test program development SME: Drive and develop and maintain test programs for HBM component validation Deliver timely test program releases aligned with validation milestones and drive code quality, reviews, and release best-practices Drive test time optimization and parallelism improvements Drive test stab

About Mach Industries Founded in 2023, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms. At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 350 employees, we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role Mach Industries is seeking a Senior Aerospace Engineer, Aerothermal & Hypersonics to own high-speed aerodynamic and aerothermal design for next-generation hypersonic and atmospheric entry systems. This role is for an engineer with 5–7+ years of experience who has taken complex aerospace work from concept through design, analysis, test, and implementation — and who can help stand up aerothermal and TPS test capability as the company scales. You will lead hypersonic vehicle shaping and aero/aerothermal trades, predict aerodynamic heating and related high-temperature flight environments, and contribute to Thermal Protection System (TPS) / heat-shield evaluation in partnership with materials, structures, and Thermal Engineers. You will also support lower-speed aero work in conjunction with other aerodynamicists when programs require it. Key Responsibilities High-speed aero and aerothermal design: Lead or co-own aerodynamic and aerothermal design activities for hypersonic and atmospheric entry vehicles — vehicle shaping, performance, stability, and thermal environment definition — and support lower-speed aero work in conjunction with other aerodynamicists when the program requires it. Aerothermal environments: Predict and analyze aerodynamic heat

Shipping the software that powers Zoox’s autonomous vehicles is an extremely challenging job. As a Software Engineer on the Core Data team, you will help build the foundational systems that capture, persist, move and retrieve the critical data generated by our fleet of robots. Our systems connect real-time vehicle software with the engineering and operational workflows requiring fleet data. This includes making critical data available for development, validation, fleet operations, incident investigation, and continuous improvement of the autonomous driving stack. You will tackle complex challenges involving high-speed data, constrained compute & storage resources, multi-host architectures, and fault-tolerant design. This role combines hands-on implementation and systems-level problem solving with opportunities to influence the long-term architecture of Zoox’s vehicle data systems. You will collaborate across the organization to define requirements and deliver practical, reliable solutions to ambiguous cross-functional problems. In this role, you will: Contribute to the technical architecture and implementation of Zoox’s on-vehicle data systems Design and develop reliable, high-performance systems for capturing, storing, retrieving, and transmitting vehicle data with strict real-time and resource constraints Own complex technical problems from initial investigation through design, implementation, validation, and rollout Collaborate across teams through requirements definition, design reviews, and code reviews Qualifications: Bachelor’s degree in computer science, engineering, mathematics, or a related field and 3+ years of professional software development experience Strong proficiency in modern C++ Experience with multithreading, concurrency, inter-process communication, or networking Strong problem-solving skills and the ability to investigate issues across multiple software and

Company Name: tastytrade Role: Staff Software Engineer, Order Handling and Ledger Team Location: Chicago, IL - Hybrid (3 days/week in office) About the Role : The tasty family of companies empowers individual investors and traders by providing educational media, intuitive and powerful trading software, high-speed order execution, competitive pricing, and innovative financial products. The diversity of our offerings and the technology that powers them give our engineers exposure to a broad set of tools and the opportunity to dig deep into specific problems. We are an ideal environment for engineers who are self-motivated, pragmatic, and genuinely enjoy creating and operating large, highly available, performant systems. Our team is lean, and our management philosophy values the autonomy of our people. At tastytrade, you'll be part of the team that builds our retail brokerage business. We care about the speed and stability of our backend systems. Our architecture evolves continually as the business grows and new technical challenges emerge, always with a focus on practicality and performance. What You'll Do : Design, build, and own the backend systems behind our order handling, ledger, and settlement flows Partner with product to scope features, build implementation plans, and oversee execution in collaboration with cross-functional teams Provide technical leadership across the team, both by leading project teams and by mentoring more junior engineers Deliver concise, constructive, and thoughtful code reviews covering design and quality, business-domain correctness, stability, and performance Monitor the external technology landscape and experiment with new tools to solve hard problems or improve the quality of existing solutions Define engineering-wide standards and guidance, and be the person colleagues across the organization seek out for critical work and decisions &nbs

We are now looking for Chip Design Internships for the Switch Silicon group. As a Chip Design Intern at NVIDIA's Networking business unit, you'll join a group of passionate engineers to implement the next generation state of the art Switch Silicon chips. In this intern position, you'll be part of a dynamic, technology-focused company while closely engaged with developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! What you'll be doing: Understand the fullchip working flow and build infrastructure for better automation, efficiency. Work in a combined design and verification team and develops test facilities for quality assurance. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. What we need to see: Pursuing BS / MS in electrical / computer engineering and related. A team player with quick learning, good communication and interpersonal skills. Fluent English (both written and spoken). Experience in RTL design or RTL verification is a plus. Strong scripting

We are now looking for a Senior Chip Design RTL Design Engineer for the Switch Silicon group. As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! What you'll be doing: Work in a combined design and verification team which develops some of the switch silicon core units. Plan and Design RTL units / blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance. Build reference models, verify and simulate chip blocks/entities according to specifications. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. What we need to see: B.Sc. in Electrical Engineering or Computer Engineering. 4&#43; years of experience in RTL design or RTL verification. Previous experience in networking - an advantage. A team player with good communication and interpersonal skills. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field. #LI-Hybrid <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Be part of a highly skilled and challenging high-speed PHY design team working on advanced technology nodes (12nm and below). Own analog sub-blocks within the PHY and drive specification, design, simulation, reliability, and mixed-mode verification. Leverage AI-enabled tools to improve productivity and decision-making. Drive layout implementation through mask designers while ensuring compliance with process rules and DFM requirements. Participate in design reviews with internal teams and customers, explaining design choices and robustness. Collaborate with cross-functional teams across multiple global locations. Create IP EDA views including Behavioral models, Verilog-A, timing views, and abstracts. Participate in silicon bring-up, characterization, and correlation of silicon results with models and simulations. Mentor and guide junior engineers. Competitive compensation and equal opportunity workplace. Required Skills Strong analog/mixed-signal CMOS circuit design experience in deep sub-micron technologies (2nm to 28nm). Experience in High-Speed Memory Interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA, etc.). Full ownership experience of at least one critical PHY sub-block such as: PLL DLL CDR High-speed Receiver with Equalization Transmitter Front-End High-Speed Data Path </ul

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Implement and integrate DFT logic at block, s

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.

Dawn Aerospace and the University of Canterbury are seeking expressions of interest from prospective PhD candidates for a number of fully-sponsored research projects in advanced aerospace engineering. Successful applicants will be enrolled as PhD students at the University of Canterbury and will undertake research projects aligned with real-world aerospace challenges at Dawn Aerospace. Candidates will be supervised jointly by University of Canterbury academics and Dawn Aerospace technical experts. This is a unique opportunity to combine doctoral research with direct exposure to one of the world's fastest-growing space transportation companies. Available Research Projects Three projects are available: Microgravity Thermofluids Analysis and Propellant Management: Research focused on fluid behaviour and propellant management in microgravity environments, supporting the development of future space propulsion systems. https://bpb-ap-se2.wpmucdn.com/blogs.auckland.ac.nz/dist/e/1107/files/2026/07/ADS-2.13-Microgravity-thermofluids-analysis-and-propellant-management.pdf Multidisciplinary Design Optimisation for Hypersonic UAVs: Research focused on advanced design methodologies and optimisation techniques for next-generation high-speed aerospace vehicles. https://bpb-ap-se2.wpmucdn.com/blogs.auckland.ac.nz/dist/e/1107/files/2026/07/ADS-2.14-Multidisciplinary-Design-Optimization-for-Hypersonic-UAVs.pdf Design and testing of novel space-efficient damping structures (Coming Soon): A third PhD project will be published shortly and applicants will have the opportunity to express interest in this project as part of the application process. NOTE: This project is not part of the Applied Doctorate Scheme Questions about a project? We recognise that prospective PhD candidates may wish to better understand the research scope, expected outcomes, funding arrangements, and supervision model before applying. If you would like additional information about any of the pro

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As part of Micron's DRAM Verification organization, you will work within a highly innovative engineering team responsible for verifying advanced memory products that power next-generation computing systems. The team develops and validates sophisticated DRAM technologies that require complex functionality verification, ultra-high-speed operation, advanced low-power capabilities, and power management features. As a DRAM Verification Engineering Intern, you will collaborate with global design and verification teams to ensure the quality and functionality of future DRAM products. You will gain hands-on experience using industry-standard verification tools, simulation environments, debugging methodologies, and advanced verification techniques while contributing to real product development efforts. This role also provides opportunities to employ Artificial Intelligence and AI Assisted tools to improve verification efficiency, analysis, and workflow automation. Responsibilities Perform verification activities including datasheet analysis, verification planning, simulation execution, coverage analysis, debugging, and results review. Support modeling and simulation efforts using industry-standard verification and circuit simulation tools. Collaborate with global design, verification, and multi-functional engineering teams to drive standardization, improve design quality, and support successful product development. Contribute to innovation in future memory technologies by applying adva