Io Module Engineer Jobs

About the Team OpenAI’s Hardware organization develops custom silicon and systems for advanced AI workloads. Our first-party accelerator team works across chip architecture, design, software, and systems to build the computing platforms that power frontier models. We are a small, dynamic team that values technical breadth, hands-on engineering, and creative approaches to building complex hardware. About the Role We’re looking for a SoC Engineer to help architect, design, and integrate OpenAI’s first-party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects our accelerator designs into complete, functional systems. This role combines architectural judgment with hands-on implementation. You’ll work closely with design, architecture, verification, and software teams throughout development, from defining subsystem requirements and integrating IP to pre-silicon validation, silicon bring-up, and post-silicon debug. You should enjoy stretching across domains, rolling up your sleeves, and doing the work needed to make a complex system function end to end. In this role, you will: Define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCI Express, Ethernet and die-to-die interfaces. Develop the microarchitecture and RTL design of subsystems supporting I/O and SoC functionality. Integrate Arm Cortex-M and Cortex-A processors, AXI/APB fabrics, and third-party controller IP, including the RTL and glue logic needed to connect these components. Develop reset and boot architectures, working with firmware and software teams to define sequencing, initialization, and survivability behavior. Incorporate debug, test, and security requirements into the SoC architecture and implementation, partnering with other silicon designers to make the silicon observable, testable, and secure. Drive PCIe and other I/O integration, including controller and PHY interfaces, high-speed SerDes,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Lead the architecture, design, integration, and silicon validation of complex analog and mixed-signal circuits for advanced DRAM products, including amplifiers, comparators, references, LDOs, charge pumps, oscillators, DLLs, I/O circuits, and on-chip monitors. Drive development of custom analog and digital IP from concept through tape-out, silicon bring-up, and production. Define architectures and design methodologies to optimize power, performance, area (PPA), reliability, yield, and manufacturability. Lead verification, modeling, parasitic analysis, silicon correlation, and design signoff across PVT and reliability corners. Guide physical implementation, including floorplanning, matching, placement, routing, and reliability-aware layout practices. Collaborate with Product, Process, Test, Probe, Assembly, and Manufacturing teams to ensure successful product qualification and high-volume production. Drive design quality, standardization, and continuous improvement through advanced CAD, modeling, automation, and verification methodologies. Mentor and develop engineering talent while providing technical leadership across projects and product generations. Drive innovation through reusable IP development, patents, technology roadmaps, and differentiated circuit architectures. Leverage engineering tools powered by AI and agentic AI workflows to improve build efficiency, accelerate verification, optimize PPA, and reduce p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to ESD Architecture Leadership & Strategy Define and own ESD architecture and protection strategy for high-speed I/O portfolios including: HBM (High Bandwidth Memory) / DDR / LPDDR PHY I/Os PCIe, USB, Ethernet, MIPI, and proprietary interfaces Lead ESD–I/O co‑design trade‑off decisions, balancing: Aggressive ESD targets (HBM / CDM / MM).Ultra‑low capacitance and leakage requirements Eye margin , jitter , bandwidth , return loss, and impedance matching Drive architectural choices for: Snapback clamps, rail clamps, diode steering networks. Triggered and advanced ESD devices (technology‑dependent). Domain isolation and sequencing protection for sophisticated SoCs Advanced Circuit Design, Modeling & Signoff : Perform and guide ESD circuit design and analysis at block and full‑chip level. Establish simulation methodologies for: Transient ESD stress (TLP‑equivalent behavior). Dynamic clamp triggering and current handling. I/O performance impact (cap loading, ringing, overshoot/undershoot. Own ESD modeling correlation: Work with device/modeling teams on compact models (dynamic R, triggering, CV behavior). Drive correlation between SPICE simulations, TLP/VF‑TLP, and silicon results. Act as the final technical authority for ESD Design reviews and signoff. Silicon Debug, Reliability & Qualification Ownership : Lead silicon-l

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Technical Program Manager to help drive the execution of complex SoC and chip-development programs supporting RISC-V CPU servers, machine learning processors, and memory and I/O chiplets. Working closely with the lead TPM and engineering owners, you will make project work visible, track owners and commitments, coordinate dependencies, surface risks, and keep teams moving toward their development milestones. This is a technical program role focused on design and development execution; it does not own engineering decisions or create or approve the project budget. Prior semiconductor experience is helpful, but candidates from software and other technical-development environments are welcome and can learn the SoC domain in the role. This role is hybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You are organized and able to turn complex discussions into clear actions, owners, priorities, and concise status updates. You take ownership of project follow-through, proactively identify blockers, and can influence technical stakeholders without relying on direct authority. You communicate firmly and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Senior Analog Design Engineer to join our High Bandwidth Memory (HBM) team. This role is responsible for the architecture, design, simulation, and silicon bring ‑ up of high ‑ performance analog and mixed ‑ signal circuits used in HBM PHYs and supporting infrastructure. The ideal candidate has deep expertise in high ‑ speed I/O, clocking, power management, and advanced ‑ node analog design, and has successfully delivered silicon to production. Responsibilities will include, but are not limited to: Design and own critical HBM analog circuits, including: High ‑ speed transmitters and receivers Clock generation and distribution (PLLs, DLLs, CDRs) SerDes ‑ related analog blocks Biasing, reference, and calibration circuits </

We are seeking a qualified Senior Software Tools Development Engineer to join our GPU SWQA team. The successful candidate will have strong experience applying AI technologies to automate test cases and a deep understanding of Windows operating systems. Extensive knowledge of GPU, CPU, SoC, x86, and ARM architectures is required, along with expertise in PC I/O architecture and common bus interfaces such as PCIe, USB, and SATA. Familiarity with specifications for general PC architecture components is a plus. What you’ll be doing: Design and implement automated tests incorporating AI technologies for NVIDIA's device driver software and SDKs on windows platforms. Build tools/utility/framework in Python, C# or equivalent which would help automate and optimize the testing workflows in GPU domain. Develop and carry out automated and manual tests, analyze results, identify and report defects. Rigorously drive test automation initiative. Build innovative ways to automate and expand our software testing. Expose defects and constraints; Isolate and debug the issue(s) and find the root cause; Contribute to the solution and drive to closure. Measure code coverage for the software under test, analyze and drive code coverage enhancements. Develop applications and tools that accelerate development and test workflows and write fast, effective, maintainable, reliable and well documented code. Generate and test compatibility across a range of products and interfaces and validate different key software applications across a test matrix designed to test both breadth and depth. Provide peer code reviews including feedback on performance, scalability and correctness. Report test coverage and Go/No-Go status for deliverables, escalate critical issues, and drive them to closure. Participate in root cause analysis and corrective actions to continuo

We are seeking a qualified Software Tools Development Engineer to join our GPU SWQA team. The successful candidate will have strong experience applying AI technologies to automate test cases and a deep understanding of Windows operating systems. Extensive knowledge of GPU, CPU, SoC, x86, and ARM architectures is required, along with expertise in PC I/O architecture and common bus interfaces such as PCIe, USB, and SATA. Familiarity with specifications for general PC architecture components is a plus. What you’ll be doing: Design and implement automated tests incorporating AI technologies for NVIDIA's device driver software and SDKs on windows platforms. Build tools/utility/framework in Python, C# or equivalent which would help automate and optimize the testing workflows in GPU domain. Develop and implement automated and manual tests, analyze results, identify and report defects. Rigorously drive test automation initiative. Build innovative ways to automate and expand our software testing. Expose defects and constraints; Isolate and debug the issue(s) and find the root cause; Contribute to the solution and drive to closure. Measure code coverage for the software under test, analyze and drive code coverage enhancements. Develop applications and tools that accelerate development and test workflows and write fast, effective, maintainable, reliable and well documented code. Generate and test compatibility across a range of products and interfaces and validate different key software applications across a test matrix designed to test both breadth and depth. Provide peer code reviews including feedback on performance, scalability and correctness. Report test coverage and Go/No-Go status for deliverables, escalate critical issues, and drive them to closure. Participate in root cause analysis and corrective actions to continuously im

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will work on the systems software strategy and execution that brings new AI silicon from first power-on to a fully integrated system running production-representative models at expected functionality and performance. You will define how software exercises and validates compute, memory, interconnect, and I/O subsystems, then build the diagnostics, automation, and observability needed to find issues quickly. This role sits at the center of silicon, firmware, platform, systems, and workload teams. You will turn hardware specifications and performance targets into an end-to-end bringup plan, drive cross-functional debug, and establish the stress and regression infrastructure that makes each new platform reliable across operating environments. In this role, you will: Contribute to the end-to-end software bringup and validation strategy for new silicon and first-party systems. Define software-driven test coverage across compute, memory, interconnect, I/O, and their system-level interactions. Build diagnostics, test automation, telemetry, and regression infrastructure that accelerate first-silicon learning and issue isolation. Lead bringup from initial silicon arrival through board and system integration, docking, runtime enablement, and model execution. Design stress tests that characterize reliability, performance, and stability across workloads and operating conditions. Translate architecture specifications and performance models into measurable acceptance crit

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's Data Center Workload Engineering team tests how memory and storage products perform in complete data center systems. We deploy customer-representative AI, database, virtualization, and software-defined storage workloads in production-class labs. We trace I/O from the application through the system to the SSD to explain performance and identify opportunities to improve it. As a Principal Systems Performance Engineer, you will lead complex performance studies from the initial question through the final recommendation. You will personally lead the hardest investigations while setting technical direction for the team. Your work will guide SSD architecture and product development and help customers get the best performance from Micron products. This is a hands-on senior individual-contributor role. Key Responsibilities Lead application performance studies on enterprise servers, GPU-accelerated systems, and data center storage platforms. Deploy customer-representative workloads across one or more areas, such as AI training and inference, checkpointing, KV-cache offload, data preparation, databases, virtualization, and software-defined and object storage. Develop test plans with clear hypotheses, realistic configurations, appropriate controls, and repeatable methods. Instrument systems and trace I/O from the application through the software and storage stack to the SSD. Measure application throughput

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. DRAM ASIC Architecture Role Overview Micron is seeking an experienced architect to drive the definition of next-generation DRAM products incorporating advanced CMOS-based logic die technologies. This role will help define how future DRAM products leverage advanced CMOS logic die technologies to enable higher levels of integration, observability, reliability, power efficiency, security, and system differentiation beyond what is achievable in conventional DRAM-only implementations. The architect will define architectures that leverage advanced logic die capabilities to complement and enhance DRAM functionality across LPDDR, DDR, HBM and future heterogeneous memory solutions. The successful candidate will architect I/O, reliability, manageability, interface, test and system-enhancement functions. The role requires strong collaboration across DRAM design, ASIC architecture, packaging, process technology, product engineering, validation, firmware, and system architecture teams. Key Responsibilities Define next-generation DRAM &#43; logic-die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms – to optimize performance, power, cost, reliability, and product differentiation. Identify and evaluate system, interface, reliability, test, management, and control functions that may benefit from advanced logic-die implementations; perform architectural tradeoff analysis coverin

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics. This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners. In this role, you will: Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic. Design mechanisms for routing, arbitration, ordering, flow con

1671 About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design , with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication. Key Responsibilities End-to-end signal integrity analysis for blade- and rack-level system architectures. Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI , I2C, etc . and related interconnects. Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE , or similar. Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes . Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology. Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance. Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions. Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware. Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field . Strong experience in signal integrity for high-speed digital systems. Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes . Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and cro

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for an experienced systems software engineer to help define and build the host software stack for our custom next-generation AI systems. You will work close to the hardware on performance-critical software, including Linux kernel drivers, high-throughput I/O paths, and system-scale networking and RDMA. This role spans architecture, implementation, platform bring-up, debugging, and performance optimization. You will work across hardware and software boundaries to make new systems usable end to end, from low-level device interfaces through userspace tooling and production validation. In this role you will: Design, implement, and debug host-side systems software for AI infrastructure, including Linux kernel drivers and supporting userspace components. Build and optimize software paths for high-throughput, low-latency communication, including RDMA and related networking functionality. Develop software around PCIe, DMA, NICs, accelerators, memory movement, and device interaction. Bring up new hardware platforms and diagnose complex issues across kernel, firmware, networking, and hardware boundaries. Build tooling for integration, testing, diagnostics, observability, qualification, and performance characterization. Collaborate with hardware, networking, and platform teams to define interfaces and integrate new capabilities. Work with external vendors where needed to integrate technologies and drive issues to resolution. Contribute across the systems sof

Job Description: We are seeking a skilled Python Engineer to join our dynamic team. The ideal candidate will be responsible for developing robust web frameworks, building backend code to efficiently serve datasets, and performing data transformations to support our data-driven applications. This role requires a deep understanding of Python, web development frameworks, data processing, and database management. Roles and Responsibilities: Core Python: Be proficient in the concepts and features of the Python language , experienced with web frameworks like Flask and FastAPI for developing RESTful APIs, and skilled in asynchronous programming using asyncio. Experience with handling concurrent connections and optimizing I/O operations. Should have a deep understanding of microservices architecture and be capable of writing clean, efficient, and maintainable code. Security Best Practices and Requirements Understanding of security practices for microservices, including authentication, authorization, and encryption. Experience with securing APIs using OAuth, JWT, and API gateways. Web Framework Development: Design, develop, and maintain scalable web frameworks using Python. Collaborate with front-end developers to integrate user-facing elements with server-side logic. Ensure the web frameworks are secure, performant, and maintainable. Have a sound knowledge of one or more web frameworks that are based on Python, such as Django, Flask, Pyramid, etc. Should have the know how to use the framework's features, such as routing, templating, database integration, authentication, testing. Object Relational Mappers (ORMs): Develop backend systems to serve datasets through APIs and other interfaces. Implement data access layers, integrating with various databases and data storage solutions. Optimize backend code for performance, scalability, and reliability. Be able to use ORMs to interact with databases using Python objects. ORMs abstract away the low-level SQL queries and provi