Io Module Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Sr Design Engineer, you will work on design, simulation, and validation of next ‑ generation High ‑ Bandwidth Memory (HBM) architectures and circuit blocks. HBM requires advanced DRAM design knowledge combined with deep understanding of 3D stacked architecture, TSV signaling, wide I/O interfaces, PHY timing, power integrity, and system co ‑ optimization with GPUs/accelerators. This role sits at the intersection of DRAM design and high ‑ performance computing, enabling future AI/ML, HPC, and advanced graphics products. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is seeking a Sr. Systems Software Engineer for the Apache Spark Acceleration group. Over the past five years GPU accelerated data processing has moved from proof of concept to production deployments. Many enterprises recognize accelerated computing is vital to handle their large data processing needs. Multi-node GPU deployments will reduce cloud computing costs and lower latency in batch ETL workloads. Apache Spark is the most popular data processing engine in data centers. At NVIDIA, we are developing an open source plugin to accelerate Spark applications on GPUs without any code changes. What you'll be doing: Enable C++ native execution of Spark operations on CUDA Develop CUDA/C++ libraries to accelerate DataFrames and I/O operations on common file formats such as Parquet, ORC and JSON Collaborate with distributed systems teams to craft solutions to distributed processing problems challenges at large scale Work with open source communities to enhance libraries like RAPIDS, CCCL and UCX through technical discussion and code contributions Provide recom

NVIDIA DGXC Storage team handles some of the fastest training and inference tasks. Every GPU cycle depends on a storage platform built to keep tens of thousands of accelerators continuously busy. It maintains exabytes of data securely and powers the largest AI workloads worldwide across cloud, neocloud, and on-prem setups. With the growth of accelerated computing, storage is essential. It can make the difference between effective GPU use and wasted potential, and between launching a frontier model on time or missing the deadline by months. We’re looking for a hands-on Storage Software Engineer to join the storage team as an individual contributor and technical lead. You will contribute to open-source parallel and distributed file systems and keep our largest GPU clusters fast, reliable, and durable. You will stay deeply hands-on: writing and reviewing production code, chasing root causes in the field, and setting the configuration and tuning standards our GPU fleets run on. This is a chance to do foundational storage engineering for the AI era at the company that introduced accelerated computing. What you’ll be doing: Contribute to open-source file systems. Contribute code to open-source parallel and distributed file systems, and distributed object storage. Upstream fixes and features, and engage directly with the upstream communities and maintainers. Serve as a hands-on storage software lead. Write and review production code yourself, and read kernel, NFS, NVMe-oF, or SPDK source when a bug requires it. Make the final technical calls on storage deliveries against measurable targets. Triage and troubleshoot at scale. Triage, troubleshoot, and root-cause large, complex storage issues across very large GPU clusters (tens of thousands of GPUs) — I/O and metadata performance, data corruption, and recovery. Validate architecture and capabilities. Validate storage architecture, capabilities, performance, and durabil

The NVIDIA DGXC Data Services team builds cloud-native systems, frameworks, and services for managing data across hybrid and multi-cloud infrastructure. We are building the next-generation data and storage infrastructure to solve some of the hardest problems in AI: storage, access, ingestion, governance, observability, and data management for exabyte-scale, high-performance GPU-based training and inference jobs. Our work gives NVIDIA teams the foundational capabilities they need to build, train, deploy, and operate AI products at scale without reinventing critical data infrastructure for every workload. What you will be doing: Build storage technologies, client libraries, and filesystem frameworks that help AI workloads access data across object stores, file systems, and hybrid cloud infrastructure. Develop high-performance storage paths for training and inference workflows, including data loading, checkpointing, caching, POSIX-style access, and object-store integration. Build observability systems that diagnose storage bottlenecks, attribute GPU idle time to I/O behavior, and expose actionable telemetry through production monitoring stacks. Improve performance, scalability, and reliability of storage systems serving massive datasets, deep directory trees, and high-concurrency AI workloads. Work closely with internal AI teams, platform teams, SRE, and operations to validate storage behavior against real workloads and production environments. Use modern software engineering practices, including AI-assisted and agentic development workflows, while maintaining high standards for design, testing, security, performance, and verification. What we need to see: BS in Computer Science, Information Sys

We're building a new generation of data center CPUs at NVIDIA — Vera, Grace, and future designs purpose-built for accelerated computing and the workloads defining infrastructure. Data analytics is one of the highest-value arenas for CPU performance, and we need someone to own NVIDIA's strategy and value proposition there! This role sits at the nexus of go-to-market, software architecture, platform architecture, performance measurement, and competitive positioning — making it a true workload strategy role, not a benchmark-running one. From TPC-H and TPC-DS methodologies to collaborative solutions with the world's leading database and analytics vendors, the scope is broad and the impact is real. We're looking for a product manager who deeply understands how CPUs win in practice and can turn that insight into roadmap decisions, customer proof points, and field-ready positioning. What you'll be doing: Taking responsibility for the workload and market approach for data analytics and data processing on NVIDIA data center CPUs — identifying priority workloads, customer scenarios, and the benchmarks and proof points that should guide the roadmap. Leading the complete lifecycle of benchmarks like TPC-H and TPC-DS: methodology, cluster and benchmarking architecture, competitive analysis, and market positioning. Translating disk, cache, memory, I/O, clustering, availability, and software behavior into concrete CPU, platform, and system requirements. Then advising architecture and platform teams on what to build and why. Building the quantitative value proposition across performance, infrastructure, software licensing, power, and TCO to position NVIDIA CPUs against challenging architectures. Working alongside external ISVs, database and analytics vendors, cloud providers, and strategic customers to verify requirements and build joint solutions and go-to-market approaches. Redefining ben

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE: We are actively seeking highly motivated engineers who excel in dynamic, small-team settings. You will get a chance to contribute to innovative product ideas that tackle challenges within massive-scale storage environments. We are looking for skilled and dynamic Software Quality Engineers with a strong focus on automation to join our team. In this role, you will be a key player in ensuring the delivery of high-quality software through rigorous testing, building and leveraging a scalable test automation, and contributions to building high-performance systems. You will actively participate in designing tests, developing and maintaining test sets and strategies, and collaborating with peers and stakeholders to achieve comprehensive test coverage. You will work closely across kernel and OS layers, gaining exposure to end-to-end system interactions, I/O paths, and performance characteristics. Strong troubleshooting skills are essential, particularly in diagnosing complex server and storage issues across hardware and software boundaries. WHAT YOU'LL DO: Designing and implementing automated tests throughout the entire lifecycle of product development and support. Creating, developing, and maintaining automated test sets and test strategies for various products. Collaborating with peers and stakeholders to identify requirements and contribute to solutions from initial test design to a comprehensive testing suite. W

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron is seeking an experienced Optical Interconnect Design Architect to define and drive next-generation optical connectivity solutions enabling future memory, AI accelerator, and high-performance computing platforms. This role will lead architecture development, technology pathfinding, feasibility analysis, and ecosystem engagement required to enable scalable optical interconnect solutions. The successful candidate will evaluate emerging photonic technologies, develop optical I/O architectures, guide proof-of-concept implementations, and collaborate with internal and external partners to identify solutions that meet future bandwidth, energy efficiency, thermal, reliability, and manufacturability requirements. The architect will influence Micron's long-term optical interconnect roadmap spanning photonic interposers, silicon photonics, optical memory interfaces, co-packaged optics, optical networking, and advanced heterogeneous integration technologies. Responsibilities will include, but are not limited to: Drive architecture explor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s High Bandwidth Memory (HBM) Design Architecture organization, where we push the limits of memory technology every day. Our team works across global, multicultural engineering groups to build next-generation HBM solutions that power AI and machine learning. We believe the best ideas come from collaboration, curiosity, and a shared drive to innovate! This role plays a critical part in ensuring the reliability of Micron’s most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design through high-volume manufacturing, working hands-on with silicon, layout, and foundry partners. If you enjoy solving deep technical problems and influencing product robustness at scale, this role offers both impact and growth. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards Enable ESD protection circuits and latch up safe layout practices across designs and technologies Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams<

We are looking to speak to candidates who are based in Sydney for our hybrid working model. Required Experience building and maintaining complex mission-critical production database systems (RDBMS or NoSQL). Coding/scripting ability in one or more languages: Java, Python, Ruby, C, C++, C#, Javascript, node.js, Go, etc. Experience working with APIs and using it to integrate with 3rd party technologies and software in the areas of security and fraud, big data analytics and AI, healthcare, content management, IoT, database performance monitoring and management; financial services, healthcare services, telco etc. Solid hands-on experience with systems engineering, including Linux performance, memory management, I/O tuning, configuration, security, networking, clusters, and troubleshooting Experience analyzing and troubleshooting issues holistically, from the application tier through the database, down to storage Troubleshooting experience with TCP/IP networking stack on OS and Hypervisor Experience using or administering one or more cloud services stacks such as AWS, Azure or GCP Hands-on experience with administering and troubleshooting NAS, SAN, local storage, multi-pathing Experience building solutions involving application workloads and use cases. Preferred Experience using or managing MongoDB preferred Experience in one or more programming languages developing applications using a NoSQL or SQL database. Strong understanding of authentication systems such as LDAP, Kerberos, AD Experience using distributed version control systems, and in particular git Experience with Kubernetes or other orchestration systems using vendor-specific Enterprise operators. Experience in working software product teams, and familiarity with product release processes from planning to release. Success Measures In 3 months, you’ll have gained a deep understanding of MongoDB and its partner ecosystem. You will complete New Hire Training. In 6 months, you will be comfortable working frontline w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Design, develop, and deliver high-quality RTL for complex DRAM, memory, and mixed-signal digital blocks, driving projects from architecture and specification through implementation handoff while meeting performance, power, area, and quality targets. Own front-end ASIC design activities, including RTL development, linting, CDC/RDC verification, functional validation, logic synthesis, static timing analysis (STA), timing constraint definition, and timing closure across multi-mode, multi-corner operating conditions. Develop, maintain, and optimize design constraints (SDC), including clock definitions, timing exceptions, I/O constraints, UPF-based power intent, and low-power implementation methodologies to achieve optimal PPA. Collaborate closely with architecture, verification, circuit design, and physical implementation teams to resolve integration challenges, improve design robustness, and ensure successful product execution. Analyze synthesis and timing reports, identify critical bottlenecks, and drive design improvements to meet performance, power, area, and schedule objectives. Chip in to the development and enhancement of design methodologies, automation frameworks, and RTL-to-GDS implementation flows, improving engineering productivity, design quality, and time-to-market. Apply strong expertise in CMOS digital and mixed-signal concepts, Verilog/System Verilog, and industry-standard EDA tools to develop scalable and reliable silicon sol

About Graphcore Graphcore is a leading innovator in artificial intelligence computing. We develop hardware, software, and data center infrastructure that provide the specialized processing and systems capabilities needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore works alongside companies developing advanced technologies. Our teams bring together AI researchers, silicon designers, hardware and software engineers, and systems architects to solve complex technical problems across the computing stack. The Opportunity As Principal Storage Architect, you will define the high-performance storage architecture for Graphcore's AI computing and data center infrastructures. You will lead the design of local and distributed storage tiers that provide the throughput, availability, and predictable tail latency required for large-scale training and inference. Working within Advanced Architecture, you will address storage requirements for saving model states, offloading key-value caches, large datasets, and high-speed data-loading pipelines. You will combine hands-on performance engineering with Principal-level technical leadership across hardware, software, networking, systems engineering, automation, supply chain, and external technology partners. What You Will Do Define the end-to-end architecture and technology roadmap for local, disaggregated, and distributed storage across Graphcore AI server and data center platforms. Design storage topologies that optimize PCIe lane allocation, network-domain placement, and data paths among CPUs, AI accelerators, memory, and storage systems. Lead the architecture of storage control-plane and data-plane solutions, evaluating commercial and open technologies against performance, resilience, manageability, and lifecycle requirements. Profile and tune the Linux storage stack, block layer, I/O schedulers, direct I/O paths, file systems, and drivers to imp

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Craft and analyze digital and analog circuits used in the development of memory products including simulating, optimizing, and floor planning DRAM circuits. Collaborate with various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to proactively craft HBM products that optimize all manufacturing functions and assure the best performance, power, cost, quality, reliability, time-to-market, and customer happiness. Innovate and integrate end-toend groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). Employer will accept a Master’s degree in Electrical Engineering, Physics, Computer Engineering, Semiconductor Engineering or a related field and 10 years of experience in the job offered or in a related field. Position requires: 1. High-speed memory design on data paths, from I/O interface to core array 2. 2. Power domain network analysis 3. Memory test architectures like MBIST and production silicon validation 4. Digital design methodologies experience including RTL design, synthesis, and physical implementation 5. ASIC design development using digital design 6. Memory core timing, latency control, and signal integrity consideration in advanced designs <p style="

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Within the larger SI R&D group, as a Principal Signal Integrity Engineer at Micron, you will be responsible for: Leading the development and analysis of high speed (HS or similar expertise) memory interfaces and power distribution networks (PDN) . Applying AI/ML and data-driven techniques to accelerate Signal Integrity / Power Integrity analysis, build optimization , and engineering decision-making. Applying automation, scripting, and AI-assisted engineering workflows to improve simulation efficiency and coverage. Representing the Signal Integrity R&D team in technical cross-functional collaborative groups , integrating with package build, silicon develop, system invent, product engineering, and marketing departments to ensure overall product performance. Driving and developing SI/PI aspects of future standards (including but not limited to JEDEC, ONFI, and IBIS) through system and product electrical capability exploration. Supporting external customers as needed. Formulating techniques and protocols for SI/PI analysis. Supporting and driving path-finding activities for IO and channel innovation to enable the next generation of memory technologies at higher speeds and densities. Minimum Qualifications PhD or MSEE, or equivalent experience, with at least 5 years of industry experience. Deep experience in Signal and Power Integrity, particularly in areas affecting I/O circui

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Everpure is seeking a Hardware Engineering Manager to lead a team developing and supporting high-performance storage systems. This role oversees the full hardware lifecycle, from design through production and customer support. The ideal candidate is a strong technical and people leader who can set direction, deliver results, and collaborate across the organization. WHAT YOU'LL DO Lead, mentor, and develop a team of hardware engineers. Set technical direction and execution plans for complex compute, storage, networking, and I/O systems. Own team delivery across architecture, schematic capture, PCB layout, eDVT, qualification, failure analysis, and production release. Harden and evolve hardware validation and qualification strategies, including automated testing, system stress testing, and coverage reviews. Drive root-cause and failure-analysis efforts for internal issues and customer escalations, ensuring corrective actions improve product robustness. Partner with Manufacturing, Operations, Test, Quality, and JDM/OEM partners to transition new hardware subsystems into production. Build scalable engineering processes, automation, documentation standards, and “Quality by Design” practices. Hire and retain top hardware engineering talent while creating a culture of accountability, collaboration, technical excellence, and continuous improvement. Communicate program status, ris

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM Design Architecture organization, where we push the limits of memory technology every day. Our team works across global, multicultural engineering groups to build next-generation HBM solutions that power AI and machine learning. We believe the best ideas come from collaboration, curiosity, and a shared drive to innovate! This role plays a critical part in ensuring the reliability of Micron’s most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design through high-volume manufacturing, working hands-on with silicon, layout, and foundry partners. If you enjoy solving deep technical problems and influencing product robustness at scale, this role offers both impact and growth. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards Enable ESD protection circuits and latch up safe layout practices across designs and technologies Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results Act as the technical interface to