Micro Optics Engineer Jobs

We are now looking for a Senior Chip Design RTL Design Engineer for the Switch Silicon group. As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! What you'll be doing: Work in a combined design and verification team which develops some of the switch silicon core units. Plan and Design RTL units / blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance. Build reference models, verify and simulate chip blocks/entities according to specifications. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. What we need to see: B.Sc. in Electrical Engineering or Computer Engineering. 4&#43; years of experience in RTL design or RTL verification. Previous experience in networking - an advantage. A team player with good communication and interpersonal skills. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field. #LI-Hybrid <

About the Team You will join the Fulfilment and Experience (F&E) team at Meesho. F&E is the operational and technological backbone powering India’s most cost-efficient, reliable, and scalable e-commerce network, serving 100M+ monthly active users. From disintermediating traditional logistics through Valmo (Meesho’s unbundled micro-entrepreneur supply platform) to driving zero-commission seller enablement and real-time speed platforms, F&E operates at the intersection of deep systems thinking, network engineering, and structural innovation. We solve industry-defining supply chain problems at a scale that few companies globally can match. About the Role This role offers a direct mandate to reshape a function that touches every single Meesho order, with full autonomy over team structure, roadmap, and how you solve the problem. It also gives you a seat at the table with senior leadership on one of Meesho's most visible 2-year bets, while allowing you to work at the intersection of scale (India's largest value e-commerce platform) and zero-to-one building. What You Will Do Order-to-delivery experience — speed, reliability, and predictability of the fulfillment promise Post-order experience — returns, refunds, and how fast/painlessly they resolve Customer support — treating support volume as a signal to fix root causes, not just a queue to clear The fast delivery network bet — reimagining what "fast" means for value e-commerce, and what infrastructure/network changes get us there A team of 10–15 — you'll build, coach, and scale a pod of builders (not just managers) What You Will Need B.Tech/MBA from a premium institute preferred 5–8 years overall experience; 2+ years in management consulting, strategy & ops, or a startup/tech environment (e-commerce or logistics preferre

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an experienced CPU Architect/Micro-Architect to drive the next generation of high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions. In this role, you will drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads. Working closely with architects, software teams, silicon designers, and external IP partners, you will translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA) while enabling future HPC/AI computing platforms. This role is ideal for an architect/micro-architect who enjoys working across hardware and software boundaries, defining next-generation compute architectures, and shaping how CPUs and HPC/AI workloads work together. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Passionate about designing next-generation compute architectures for AI, HPC, and large-scale datacenter systems. Experienced in CPU

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a member of the ASIC Design team, you will work on design tasks for Micron's next generation of solid-state drive controllers. You will be involved in various phases of the ASIC design process, from concept to production silicon. This includes writing micro-architecture specifications, implementing RTL design, collaborating with the verification team to fully validate the design, delivering a gate netlist to the back-end implementation team to meet timing and physical constraints, and developing scripts to improve the design process. The ideal candidate is highly motivated, detail-oriented, and possesses excellent documentation and communication skills. Strong collaboration skills and a commitment to completing tasks with high quality are essential. This role additionally expects familiarity with AI assisted engineering tools to improve productivity, accelerate debugging, and enhance documentation quality, while ensuring responsible and secure usage. Responsibilities: Design, implement, and debug complex logic designs. Integrate your IP into larger and more complex IPs. Support front-end integration activities such as Lint, CDC, Synthesis, and ECO. Implement design automation using Python or other programming languages. Collaborate with SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams. Work closely with software and systems teams to ensure high-quality system integration.<

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and

A World-Changing Company Palantir builds the world’s leading software for data-driven decisions and operations. By bringing the right data to the people who need it, our platforms empower our partners to develop lifesaving drugs, forecast supply chain disruptions, locate missing children, and more. The Role The Palantir Design Team is responsible for the human experience of using our software. Our team is growing rapidly, but we're committed to creating a tight-knit team environment that fosters trust, integrity, empathy, and growth. We work together in realizing a shared product vision, and regularly give feedback and critique to each other. Designing at Palantir is a varied experience. On a given day, you might be: leading a design sprint for your product team; designing a micro-interaction to make a complex analytical task feel simple; and/or advocating for UX consistency by creating flexible, reusable UI components. Core Responsibilities As a Product Design intern, your responsibilities look similar to a full-time designer, with the resources, stability, and mentorship of an established tech company. You’ll work on product teams with minimal supervision and own end-to-end execution of real product features. You will work with fellow Designers, Product Managers, Developers, and Forward Deployed Engineers to refine and evolve the quality of Palantir products. Interaction and visual design . You'll be involved at every stage of design work. You'll help define early product concepts, flesh out the high-level workflow and micro-interactions of a feature, and execute on a crisp and effective visual design. You should have experience designing and prototyping using tools such as Figma. User research . We frequently do informal user research, and value people who can be flexible with research processes and methodologies to achieve the right outcome. You'll often visit customer offices to interview and learn

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Responsibilities Perform electrical and physical failure analysis for device anomalies, customer returns, and qualification failures. Apply advanced FA tools including FIB/EDX, SEM, Ion Millers, CSAM, 2D/3D X-ray, Emmi systems, micro-prober and bench tester. Analyze test data failures using Bash/Python scripting in a Unix environment. Analyze electrical signatures and physical defects to resolve failure mechanisms. Collaborate with process owners and Product teams to drive improvement actions. Develop and implement new FA techniques to reduce turnaround time and enhance accuracy. Drive continuous improvement initiatives and embrace standards for FA workflows. Ensure strict consistency to lab safety protocols and chemical handling guidelines. Maintain &#43;6S standards in the FA lab. Prepare detailed FA reports and maintain accurate records for traceability. Present findings to requestors, MRB and multi-functional teams. Provide guidance to FA technicians and lead workload distribution. Work closely with vendors for tool upgrades and capability improvements. Utilize AI-enabled tools and digital solutions to accelerate failure analysis investigations, improve problem-solving efficiency,

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize flip chip attach processes including bump formation, placement, reflow, and underfill for high-performance semiconductor packages. Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps) and substrate pad finishes for robust interconnect performance. Drive package integration from die to substrate, ensuring alignment, coplanarity, and yield optimization. Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding, head-in-pillow, and interconnect defects. Collaborate with substrate vendors, OSATs, and internal teams to define design rules (pad pitch, bump pitch, keep-outs, stack-ups). Lead process development for reflow profiles, flux selection, cleaning, and underfill dispense/cure. Perform root cause analysis of assembly and reliability failures using cross- sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manufacturing teams to ensure robust package performance from concept through high-volume production. Required Technical Skills: Strong experience in flip chip packaging and assembly processes for semiconductor devices. Deep understanding of bumping technologies (solder bumps, Cu pillar, micro- bumps) and UBM/metallization systems. Experience with underfill materials, dispense techniques, flow behavior, and cure processes. Understanding of thermo-mechanical behavior in flip chip assemblies (CTE mismatch, warpage, solder

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out). This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities Own end-to-end bump interconnect development for both ubump (micro-bump) and C4 processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip attach for high-performance semiconductor packages. Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys) interconnects, including UBM selection and pad finish specifications for both chip-side and interposer capture pads. Develop and own design rules for bump interconnects including pitch, bump diameter, standoff height, keep-outs, and land pad geometry for both the chip side and interposer or substrate capture pads. Lead RDL (redistribution layer) process development including electroplating of Cu RDL traces, via fills, and pad finishes; define RDL design rules for line/space, via diameter, and layer stack-up to meet electrical and reliability requirements. Collaborate with OSATs and bumping foundries to qualify ubump and C4 bumping processes, drive design rule alignment, and manage process transfers into production. Evaluate and mitigate bump interconnect assembly risks including non-wet opens, voiding, head- in-pillow, intermetallic growth, and joint fatigue failures across both ubump and C4 interconnect types. Perform root cause analysis of assembly and reliability failures using cross-sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Micron’s Memory Systems Engineering team and contribute to the development of premier digital and mixed-signal foundations for our high-bandwidth memory (HBM) products. This position offers an outstanding chance to work intimately with multiple engineering areas, guaranteeing the smooth integration and implementation of HBM base die. Join a motivated team committed to delivering robust first-pass silicon that meets our strict bandwidth, latency, power, and reliability objectives! Responsibilities Assist in defining and carrying out digital micro-architecture for HBM base-die subsystems, covering channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance counters, and reliability features. Translate system requirements into timing, power, and area considerations by partnering with physical layer and system architects, and help maintain interface specifications for bus protocols, clock-domain crossings, and reset strategies. Implement and integrate synthesizable SystemVerilog RTL, including multi-channel logic, interrupts, events, register maps, scan hooks, and design-for-test interfaces, while supporting clean integration and ECO flows. Collaborate with design verification teams to support verification planning, coverage goals, CDC/RDC checks, and debugging of RTL, testbench, and gate-level issues. Support silicon bring-up and post-silicon validation through debug enablement, issue correlation to RTL or architecture, and col

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert in physical design practices used to optimize PPA Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area

About Us: Paytm is India's leading mobile payments and financial services distribution company. Pioneer of the mobile QR payments revolution in India, Paytm builds technologies that help small businesses with payments and commerce. Paytm’s mission is to serve half a billion Indians and bring them to the mainstream economy with the help of technology. About the role: As an Senior Engineering Manager, you will be developing the detailed design structure, implementing the best practices and coding standards, leading a team of developers for successful delivery of the project. You will be working on design, architecture and hands-on coding. Requirements: 9 to 13 years in Technical development with 5+ years in Providing technical leadership for high performance teams. Work closely with business and product teams to understand the requirements, drive design, architecture and influence the choice of technology to deliver solutions working closely with architects and leadership team. Build robust, scalable, highly available and reliable systems using Micro Services Architecture based on Java, Spring boot. Improve Engineering and Operational Excellence by identifying and building the right solutions for observability and manageability. Keep the tech stack current with the goal to optimize for scale, cost and performance. Migrate workloads to public cloud. Attitude to thrive in a fun, fast-paced environment. Serve as a thought leader and mentor on technical, architectural, design and related issues. Proactively identify architectural weaknesses and recommend appropriate solutions. Preferred Qualification : Bachelor's/Master's Degree in Computer Science or equivalent Skills that will help you succeed in this role: Tech Stack: Lang: Java, DB: RDBMS, Messaging: Kafka/RabbitMQ, Caching: Redis/Aerospike, Micro services, AWS. Strong experience in scaling, performance tuning & optimization at both API and storage layers Hands-on leader, and problem solver with a passion for e

About the Team You will join the Fulfilment and Experience (F&E) leadership team at Meesho. F&E is the operational and technological backbone powering India’s most cost-efficient, reliable, and scalable e-commerce network, serving 100M+ monthly active users. From disintermediating traditional logistics through Valmo (Meesho’s unbundled micro-entrepreneur supply platform) to driving zero-commission seller enablement and real-time speed platforms, F&E operates at the intersection of deep systems thinking, network engineering, and structural innovation. We solve industry-defining supply chain problems at a scale that few companies globally can match. About the Role As a Director within F&E, you will be a critical anchor shaping how buyers and sellers experience the platform and how efficiently and reliably it runs. This is a highly generalist leadership role designed for a strategic problem-solver who can navigate seamlessly between long-term strategic transformation and large-scale, metrics-driven execution. Rather than being confined to a single vertical, you will own one (and over time, potentially more than one) of Meesho's most critical F&E charters. Depending on where the business needs you most and where your strengths lie, this could be any of: Valmo Platform & Network Economics: Scale Meesho’s low-cost logistics ecosystem. Drive unbundled logistics innovation across Valmo Airhubs (first/last mile), Valmo Bases (sortation/middle mile), and Captains & Pilots (franchise partners and delivery execution) to reduce Cost-Per-Delivery-Order (CPDO) while improving SLA predictability. Speed Platform & Valmo Express: Build product and operational levers that make fast delivery a structural advantage. Drive program adoption (e.g., "FAST" badges, early-morning cutoff SLAs, dedicated FE pickups) to lower RTO (Return to Origin) and cancellation rates. User Experience & Buyer Trust: Architect end-to-end pre- and post-order journeys for India’s price-sensitive Tier-2+ consumer

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 8-12 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root cau

A World-Changing Company Palantir builds the world’s leading software for data-driven decisions and operations. By bringing the right data to the people who need it, our platforms empower our partners to develop lifesaving drugs, forecast supply chain disruptions, locate missing children, and more. The Role The Palantir Design Team is responsible for the human experience of using our software. Our team is growing rapidly, but we're committed to creating a tight-knit team environment that fosters trust, integrity, empathy, and growth. We work together in realizing a shared product vision, and regularly give feedback and critique to each other. Designing at Palantir is a varied experience. On a given day, you might be: leading a design sprint for your product team; designing a micro-interaction to make a complex analytical task feel simple; and/or advocating for UX consistency by creating flexible, reusable UI components. Core Responsibilities As a Product Design intern, your responsibilities look similar to a full-time designer, with the resources, stability, and mentorship of an established tech company. You’ll work on product teams with minimal supervision and own end-to-end execution of real product features. You will work with fellow Designers, Product Managers, Developers, and Forward Deployed Engineers to refine and evolve the quality of Palantir products. Interaction and visual design . You'll be involved at every stage of design work. You'll help define early product concepts, flesh out the high-level workflow and micro-interactions of a feature, and execute on a crisp and effective visual design. You should have experience designing and prototyping using tools such as Figma. User research . We frequently do informal user research, and value people who can be flexible with research processes and methodologies to achieve the right outcome. You'll often visit customer offices to interview and learn