Packaging Value Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products. Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules. Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The PDE API Process Integration (PI) Engineer is responsible for driving process integration excellence for Advanced Packaging products, including High Bandwidth Memory (HBM) products across sites during New Product Introduction (NPI) . This role ensures robust process readiness, yield ramp, and cross‑module integration across Front-end to Assembly interactions , PWF, Assembly, and Test , enabling successful execution of HBM technology roadmaps. The PI Engineer works cross‑functionally with different cross-functional teams including Fab, Assembly, Test, Yield, Quality, and central engineering teams to identify risks early, resolve complex integration issues, and deliver NPI milestones on time. Job Responsibilities Technical Leadership Serve as the Process Integration Subject Matter Expert, owning end‑to‑end integration across PWF, assembly, and test from NPI through sustained HVM Define PI technical direction, integration frameworks, and success criteria for HBM programs Lead process characterization strategy, window definition, and systemic yield improvement Resolve complex yield, reliability, and performance issues through deep technical analysis and integration expertise Drive resolution of high‑impact, ambiguous, cross‑site integration challenges affecting ramp, quality, or business commitments Anticipate risks early and define mitigation strategies across programs and sites

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Summary The DRAM Packaging organization is responsible for developing and delivering advanced memory packaging solutions that enable Micron’s next generation products. The team partners across design, technology development, manufacturing, quality, supply chain, and external ecosystem partners to drive innovation, accelerate product development, and deliver industry-leading packaging technologies that support markets including AI, cloud, mobile, automotive, high-performance computing, and data centers! Position Overview As the Director of DRAM Packaging, you will lead the strategy, development, and execution of advanced packaging solutions across Micron's memory portfolio. You will define technology roadmaps, drive innovation in next-generation packaging architectures, and build a high-performing global engineering organization. This executive leadership role combines technical expertise, business strategy, customer engagement, and digital transformation to accelerate innovation, improve organizational effectiveness, and strengthen Micron’s competitive position. Responsibilities Define and execute long-term DRAM packaging strategies that support future product, technology, and business objectives Lead development and deployment of advanced packaging technologies, including HBM, LPDRAM, DDR, 2.5D/3D integration, heterogeneous integration, chiplets, and next-generation interconnect solutions Drive adoption of AI, machine learning, advanced analytics, and digital engineering

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: The Advanced Packaging Technology Development (APTD) team at Micron leads the creation of powerful memory and storage solutions that power the AI era. We work hands-on with global R&D groups, suppliers, and manufacturing teams to turn breakthrough ideas into real, production-ready technologies. We thrive on innovation and collaboration! Position Overview: This role will be part of a highly collaborative and innovative Advanced Packaging Wafer Edge Trim, Backgrind & Thinning R&D team, responsible for developing and scaling critical mechanical wafer processing modules. This role offers broad opportunities for technical innovation, early stage pathfinding, and ownership of process solutions that enable next generation advanced packaging technologies. You will work closely with process integration and adjacent process areas including Bonding/De-bonding, CMP, Wet Etch, Lithography, Assembly, and Test, while driving process readiness to meet bold program, performance, and yield targets. Responsibilities: Develop and optimize wafer edge trim, backgrind, and thinning processes to meet the mechanical, electrical, and reliability requirements of Micron’s advanced memory products. Improve process capability, yield, cost efficiency, and wafer integrity through data‑driven optimization and equipment or consumable innovation. Conduct root‑cause and failure‑mode analyses to understand wafer damage mechanisms such as edge chipping,

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Package Pathfinding Architect We are the team defining the future of packaging of complex memory systems! Our Package pathfinding and Architecture organization sits at the intersection of silicon, packaging, systems, and customer needs—turning complex scaling challenges into technologies that power next‑generation platforms, through cutting edge packaging technologies. If you enjoy working on problems with real industry impact, look no further. This is a technical pathfinding role driving forward-looking packaging technology for next generation memory systems from datacenter to edge-AI. You will leverage understanding of end‑to‑end memory system architectures, to guide long‑term package technology direction, and partner with customers, to build innovative ideas into scalable products. You will interface between package process technology, materials, electrical, thermo-mechanical and system performance areas to guide the package strategic roadmaps for Micron. Main Responsibilities: Define next‑generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance. Lead cross‑stack co‑optimization across silicon, package, board, and system with package ce

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. An Operations Improvement Engineer is a key member of the Operations Improvement (OI) Team. This role is responsible for driving performance optimization across PWF, Assembly (HBM, advanced packaging) and T est Operations by identifying improvement opportunities in output, cycle time, cost, and efficiency. It involves applying industrial engineering principles to enhance core manufacturing functions such as line management, production planning, scheduling and dispatching. Additionally, the role supports factory automation initiatives by exploring and implementing innovative solutions that streamline processes and reduce variability. Key Responsibilities: Identify and analyze optimization opportunities within PWF, Assembly (HBM, advanced packaging) and Test

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Position Summary As an APTD MTS (Member of Technical Staff) based in Taiwan, you will lead and develop the IoT engineering team delivering Industrial IoT (IIoT) and machine vision solutions to support advanced packaging technology development and factory enablement. You will set technical direction and priorities, drive execution from proof-of-concept through deployment, and build scalable, secure solutions that improve quality, productivity, and early risk detection. You will partner cross-functionally to translate manufacturing needs into measurable signals, robust data pipelines, and actionable insights, while building a culture of safety, accountability, and continuous learning. Key Responsibilities Lead, coach, and develop the IoT engineering team; set clear expectations, provide regular feedback, and build growth plans aligned to APTD needs. Own team execution: define goals/KPIs, prioritize the IoT roadmap, assign ownership, and ensure high-quality, on-time delivery from concept to factory deployment. Drive end-to-end IIoT solution development: sensing strategy, edge compute, connectivity, data ingestion/storage, monitoring, and sustainment (including data quality and traceability). Drive machine vision solutions: guide hardware selection (cameras/optics/lighting), image acquisition strategy, algorithm approach, performance validation, and deployment readiness. Partner with process, equipment, automation, quality, and IT/data platform stakeholders to tra

About the Role We are seeking a Strategic Finance Lead to help lead the economics of our AI products. In this role, you will be a key partner to our product, inference, and data teams, providing financial expertise to optimize model spend and drive pricing and margin decisions. In this role, you'll develop deep expertise in the unit economics of AI products, from per-request serving cost to consolidated product-level margin across our portfolio. You'll build the models that inform Perplexity's pricing, packaging, and model-deployment decisions, own the product-margin methodology that reconciles revenue and inference cost from production data, and translate complex model economics into clear financial narratives for leadership. This is a high-impact role for someone who thrives at the intersection of finance and AI product strategy, and who is energized by building frameworks from scratch in a fast-moving environment. This position is based in San Francisco and requires in-person attendance 2-3 days per week. Key Responsibilities Finance lead for inference and model spend, including budgeting, monthly forecasting, variance analysis, and financial plan maintenance Build and maintain product-margin models across the product portfolio, reconciling revenue, serving cost, and gross margin from production usage data Develop deep expertise in model provider contracts, pricing structures, and cost drivers, and surface optimization opportunities across the model portfolio and routing mix Serve as subject matter expert for product unit economics, owning source of truth on cost per request, margin by product and tier, and customer-segment and feature-level economics Own the consolidated model-cost forecast, translating product roadmaps and model transitions into forward-looking spend and margin trajectories Analyze the margin impact of pricing, packaging, and model-deployment decisions, distilled into a framework for product and pricing strategy Partner closely with product, in

About the team OpenAI’s Applied AI organization turns our latest model capabilities into products used by hundreds of millions of consumers, developers, and organizations worldwide. Our teams build the product experiences and platform foundations behind ChatGPT, Codex, our API platform, and offerings for businesses, enterprises, educational institutions, and other customers. Financial Engineering powers how customers purchase, access, and pay for these products. We build the systems behind pricing and packaging, checkout, payments, subscriptions, usage-based billing, credits, entitlements, invoicing, and the broader order-to-cash lifecycle. Our work spans consumer subscriptions, self-serve businesses, sophisticated enterprise agreements, developer usage, and emerging monetization models. These systems sit at the intersection of product experience and financial infrastructure. They must make it easy for customers to adopt OpenAI products while maintaining strong guarantees around correctness, reliability, security, reconciliation, and auditability. We partner closely with Product, Data Science, Finance, Accounting, Risk, Operations, and Go-to-Market teams to launch new offerings and build a financial platform that can evolve with OpenAI’s rapidly growing product portfolio. We are looking for an experienced engineer to help architect and build the next generation of these systems. In this role, you will: Have 5+ years of professional software engineering experience building and operating production backend, platform, or distributed systems. Have strong fundamentals in API design, data modeling, storage systems, transactional workflows, and event-driven architecture. Have experience building systems where correctness, reliability, observability, security, or data integrity are especially important. Are comfortable owning ambiguous, business-critical problems from initial definition through launch and long-term operation. Bring a product-oriented mindset and care about

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: The Advanced Packaging Technology Development (APTD) department at Micron Technology is at the forefront of innovation, driving the advancement of memory and storage Interconnects and Packaging solutions that transform how the world uses information. Micron is dedicated to developing innovative processes and technologies that enable the creation of next-generation semiconductor products which drive the AI revolution. By collaborating closely with our global R&D, equipment and materials suppliers, and manufacturing teams, we ensure the efficient development, transfer and implementation of new technology nodes, maintaining Micron's leadership in the industry. Position Overview: As a Process Engineer on the APTD Bonding team, you will be responsible for starting up, developing, and optimizing processes to improve product quality and reliability. This entails working on process yield and productivity improvement, cost reduction, and risk management as well as resolving manufacturing line problems. You will also be required to identify, diagnose, and resolve assembly process-related problems by applying failure analysis, FMEA, 8D or SPC/FDC methodology. Responsibilities: Develop new or modified process formulations, define equipment requirements and specifications, and review processing techniques and methods Identify, diagnose, and resolve assembly process related problems Coordinate and complete process, equipment, and material evaluati

Job Details: Job Description: As one of the world's largest semiconductor manufacturers, Intel is committed to advancing every aspect of semiconductor technology, from process development and manufacturing to advanced packaging and reliability characterization. Employees within Intel Foundry are part of a global network spanning technology development, manufacturing, assembly, test, and quality organizations across both front-end silicon and advanced packaging facilities. You will join the Foundry Lab Network (FLN), a key organization within Foundry Quality, Reliability, and Labs (FQRL), located at Intel's growing Chandler, Arizona site. This site serves as the technology development hub for Intel's most advanced packaging technologies, including Hybrid Bond Interconnect (HBI), Embedded Multi-die Interconnect Bridge (EMIB-T), glass substrates, Foveros, and future advanced packaging innovations. FLN is actively expanding its laboratory capabilities and capacity to support Intel Foundry's roadmap, enabling faster technology qualification and accelerating development cycles through Quick Turn Monitoring (QTM) solutions that significantly reduce time-to-data. As the Stress Test and Reliability (STaR) Back-End Laboratory Manager, you will play a critical leadership role within FLN. You will partner closely with Packaging Technology Development, Quality and Reliability, and Failure Analysis teams to establish and enhance laboratory capabilities that support qualification and certification of next-generation packaging technologies and products. This position offers a unique combination of people leadership, technical problem solving, and organizational strategy. You will lead a team of 7-10 talented engineers, spearhead cross-functional efforts to resolve complex reliability and technology challenges, drive strong quality and operati

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we're not just designing chips. We're building the physical architecture that powers artificial intelligence, accelerates cloud computing, enables autonomous vehicles, and connects the world through mobile and edge devices. Every breakthrough in AI — from large language models to next-generation data centers — runs on memory. And every bit of that memory lives inside a package that someone like you designs! We're looking for a Senior Package Design Engineer who is passionate about sadvanced semiconductor packaging and ready to lead at the intersection of silicon, system, and scale. This is a high-impact, highly visible role where you'll work across the full product lifecycle — from early-stage co-design with silicon teams all the way to High Volume Manufacturing (HVM). If you thrive where precision meets innovation, where your decisions shape products reaching millions of users worldwide, and where your expertise directly influences how the AI era unfolds — this role is for you! Responsibilites: Lead Co-Design from Silicon to System - Partner with silicon design, Business Units, customers, and package architecture teams to define new product concepts from the earliest stages of chip development - Optimize die floorplans, interconnection schemes, and package architectures — from concept to HVM - Drive trade-off studies and architecture decisions for advanced DRAM products targeting AI/D

We Creative Zone, We print high-quality RFID cards for offices, schools, colleges, hotels, hospitals, apartments, gyms, and businesses. Our durable PVC RFID cards are compatible with most access control and attendance systems, offering excellent print quality, long-lasting performance, and professional finishing. Services Offered RFID Smart Card Printing Premium PVC RFID Cards Attendance Cards Hotel Key Cards Access Control Cards Custom RFID Card Printing Why Choose Us? Professional Design Support | Competitive Prices Quick Production | Reliable Quality Secure Packaging | Online Ordering Excellent Customer Support https://www.instagram.com/creativezoneidcards/ https://www.facebook.com/share/1BFV59CmYh/ Contact: MULLAI 501 Creative Zone –Bangalore

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In the Technology Development — Advanced Modeling & AI Solutions (AMAIS) organization, you will be part of a multidisciplinary team developing next-generation Digital Twins, predictive modeling solutions, and AI-driven technologies that accelerate advanced memory development and manufacturing excellence. You will create predictive digital representations of semiconductor processes, materials, structures, equipment, and products across DRAM, NAND, and advanced packaging technologies including HBM. Leveraging physics-based modeling, computational methods, machine learning, GenAI, large language models (LLMs), and agentic AI frameworks, you will enable technology co-optimization, design-space exploration, process optimization, yield improvement, and accelerated technology learning. Working at the intersection of engineering fundamentals, manufacturing data, and digital engineering, you will develop scalable predictive and prescriptive solutions that connect process, structure, performance, yield, reliability, and cost. This role offers the opportunity to influence critical technology decisions, drive fab-technology co-optimization , and advance Micron's leadership in data-driven semiconductor memory innovation. Qualifications: Independence – be comfortable executing activities and needs Experience in algorithm development, numerical methods, and scientific computing Solid experience with Plasma, FPM, HAR etching, and MC modeling Experience with Wet Pr