Packaging Value Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: A senior advanced assembly technology development engineer is responsible for introducing new technology to enable next generation packaging. This position engaged latest stacking/flip chip technology, advance packaging material and work on new process set up, process/ packaging characterization and process transfer from TD phase to high volume production to meet development milestone. This position required high motivation and operation skill to build DOE sample and fulfill customer requirement sample as well as cooperate with Material engineer, Bumping, PI, NPI, quality and manufacturing team to ensure process transfer successfully. Responsibilities Explore new technology on semiconductor industry such as flip chip, TCB and hybrid bonding process equipment and packaging material. Provide plan and resource requirement to enable new technology. Set up DOE plan and execute. Build sample and perform data analysis skill. Lead efficiency trouble shooting skill to improve process. Prepare documentation for process transfer from TD to HVM Review process stability by FDC, SPC and test result. Self-motivated and capable of working independently, proactively identifying opportunities and driving projects with minimal direction. <span

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Packaging Technology Development (APTD) department at Micron Technology is at the forefront of innovation, driving the advancement of memory and storage Interconnects and Packaging solutions that transform how the world uses information. Micron is dedicated to developing innovative processes and technologies that enable the creation of next-generation semiconductor products which drive the AI revolution. By collaborating closely with our global R&D, equipment and materials suppliers, and manufacturing teams, we ensure the efficient development, transfer and implementation of new technology nodes, maintaining Micron's leadership in the industry. As a Realtime Defect Analysis (RDA) Technology Development Engineer in APTD, you will learn how to use pioneering defect detection equipment and processes to solve issues and drive improvement. The goal of this position is to accelerate cycles of learning and technology transfer in Technology Development (TD). We're seeking an engineer who is passionate about creative problem solving and finding innovative solutions. This position will provide the opportunity for you to collaborate with engineers in process integration, process development, data science, and yield analysis within and outside of TD. Your ideas will impact the team globally! We need someone who will investigate process anomalies through root-cause analysis, data manipulation, and correlations. You will be expected to support experimentation, data analysis, baseline health metrics, and systema

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high-performance memory! As an SMTS/DMTS HBM ESD/Latch-Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system-level ESD challenges. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging Establish ESD/LUP standards, rule decks, and signoff criteria Drive correlation between d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As part of APTD SG Technology Development Process Integrator, you will be responsible for developing advanced packaging process solution and ensure New Process, New Equipment, New Material and Path finding activities success for all adv pkg products in Micron. To lead new Technode process readiness and improving the yield, quality and reliability with process characterization and optimization and new materials, machines & technologies introduction. You will need to have understanding of Frontend Process, packaging requirements, chip package interaction, equipment understanding and process technology in the industry. The ability to enable best technology for New Technode with packaging requirements. You will also be required to drive & collaborate with cross functional teams to resolve process related problems. Ensure smooth transition from new process development, 1st qualification success to small volume production launch Development and Qualification of new packaging process, material, equipment and technology solutions to meet new Technode requirements and schedule Perform CPI NUDD, process TRA, risk mitigation execution and process recipe readiness prior Silicon arrives and ensure 1st pass rate. Qualify new process/technology/equipment/materials Technical capability Identify path finding opportunities for Micron's technology leadership with BIC time to market, continuou

SYNOPSIS: The Manufacturing Co-Op role is designed for high school juniors and seniors seeking entry-level experience in production. As a Co-Op, you will perform various tasks associated with assembly, ensuring the quality of your work. This position offers the flexibility to work in teams, small batch production, or flow lines. This opportunity aims to provide valuable hands-on experience in production, with the potential for future apprenticeship opportunities. Projected start date: Fall 2026 RESPONSIBILITIES: May be required to operate various hand tools and other equipment. Has the ability to read and understand production documentation and drawings. Understands basic electronics concepts and can follow wiring schematics. Performs final assembly, electrical testing, and packaging of various assemblies Performs screening and separation of various parts Responsible for recording assembly time data and completion of all associated routing, quality inspections, and other related forms Performs miscellaneous assigned tasks Assist in other Production areas as needed Focus on increasing productivity in all activities Follow necessary PPE requirements, appropriate ISO specifications and company procedures. Performs other related duties as assigned. QUALIFICATIONS: Must be a junior or senior in high school. Must be at least 16 years of age by the start of the role. Strong organizational skills. Ability to read and comprehend English written production documents. Basic computer skills. Consistently demonstrate a positive attitude toward all aspects of work Apply effort and energy to lifelong learning and strive to continually grow Knowledge of and desire to work in a production environment. ESSENTIAL JOB FUNCTIONS: Must be willing to be cross trained in several assembly functions to meet constantly changing production requirements Must be willing to be moved into various work centers in order to meet production requirements or where skills best serve departm

About Us: Comfrt is one of the fastest-growing direct-to-consumer brands, dedicated to blending mental wellness, inclusivity, and elevated comfort into every piece we create. Our mission goes beyond clothing — we strive to build a community where everyone feels supported and seen. About the Job: We're looking for a talented Art Manager to help define and evolve the visual language of Comfrt across every product category. This role will partner closely with the Design leaders to shape a distinctive and ownable brand aesthetic through graphics, print, pattern, branding, packaging, and storytelling across apparel, home, accessories, and future lifestyle categories. From seasonal collections to special collaborations, you'll help bring the Comfrt vision to life while ensuring every graphic expression feels cohesive, elevated, and unmistakably Comfrt. Responsibilities: Partner closely with the Design Directors to help define, evolve, and maintain the unique visual identity of the Comfrt brand across all product categories. Create original graphics, artwork, branding systems, prints, patterns, typography, and seasonal visual concepts across apparel, home, accessories, packaging, and future lifestyle products. Lead the development of seasonal graphic stories that create a cohesive visual language across collections. Design branding, logos, artwork, and creative assets for collaborations, licensed collections, and co-branded partnerships while ensuring every partnership still feels authentically Comfrt. Develop graphics across a wide range of apparel categories, including logo, licensed, non-logo, placement, repeat, novelty, and specialty graphics. Design packaging, trims, labels, hangtags, and other branded touchpoints that elevate the overall customer experience. Collaborate with Product Design, Production, Marketing, Brand, and Creative teams to bring concepts to life from initial idea through final production. Identify and interpret emerging fashion, graphic, cult

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Technology Development (TD) department at Micron Technology leads innovation. It drives the advancement of data retention and storage systems that change how the world uses information. The team develops next-generation semiconductor processes and technologies and works closely with global R&D and manufacturing teams to bring innovative solutions from concept to production. Join a collaborative environment where you will help shape the future of semiconductor technology while working alongside experienced engineers and technical leaders. Position Overview As a Process Integration Engineer in Advanced Packaging Technology Development (APTD), your role includes developing advanced packaging approaches and linking technologies. You will contribute to their integration in future semiconductor products. Working in a highly collaborative R&D environment, you will support process development, technology evaluation, and qualification activities while gaining hands-on experience with modern semiconductor technologies. This role provides an excellent opportunity for engineers who are passionate about innovation, problem-solving, and continuous learning. Responsibilities Support the development, characterization, and integration of groundbreaking packaging and interconnect solutions for next-generation semiconductor products. Collaborate with multi-functional engineering teams to analyze process data, solve technical challenges, and improve technology performance. Participate in e

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description Position Summary As an IoT Engineer, Engineer based in Singapore, you will design, build, and deploy Industrial IoT (IIoT) and machine vision solutions to support advanced packaging technology development and factory enablement. You will implement hands-on engineering work from proof-of-concept through deployment and sustainment, contributing to scalable and secure solutions that improve quality, productivity, and early risk detection. You will collaborate cross-functionally to translate manufacturing needs into measurable signals, robust data pipelines, and actionable insights, while operating with a strong safety mentality and a bias for practical, reliable delivery. Key Responsibilities Develop and deploy IIoT solutions end-to-end: sensing strategy, edge compute, connectivity, data ingestion/storage, monitoring, and sustainment (including data quality and traceability). Build machine vision solutions: support hardware selection (cameras/optics/lighting), image acquisition strategy, algorithm development, performance validation, and deployment readiness. Work with process, equipment, automation, quality, and IT/data platfor

Who we are Lab37 Robotics , is a technology company focused on the development and deployment of robots designed specifically for direct-to-customer food production. Our mission is to revolutionize the food industry by creating innovative robotic solutions that enhance efficiency, quality, and customer satisfaction. We are passionate about pushing the boundaries of technology to deliver cutting-edge products that meet the evolving needs of our clients. Role Overview You love designing, prototyping and testing new brands at speed. Given a solid brief, you can generate a full identity system fast — logo, color, type, packaging, menu, digital — without sacrificing craft. You're a maker first, with the strategic sensibility to know when the design is doing its job and when it isn't. You’re a brand world native and stay on top of what’s trending. What you’ll do Own brand direction: produce mood boards and brand synopsis that define the visual and narrative identity Lead brand naming, brand story, and logo/iconography — go from concept brief to full identity system Execute component photography and hero imagery — build the visual library that powers AI asset generation and marketplace listings Produce the full OFO asset pack (backgrounds, thumbnails, variants) and marketing assets (website, social, merch) Build and maintain a design system and templating toolkit so assets can be produced at scale Support digital onboarding and launch with platform-ready creative Work in tight sprints — expect fast feedback cycles and fast iteration What we are looking for 3+ years of brand design experience — portfolio that shows full identity systems, not just logos Experience creating in other mediums beyond static design, including photography and video Fast. You ship. You don't get precious. Strong typography and layout fundamentals Experience designing for food / hospitality / CPG (understanding of packaging, menus, and food-adjacent visual language)

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Principal Layout Designer in the Next-generation HBM Architecture Team , you will drive layout for 3D-stacked, high-performance memories. Apply your knowledge to deliver high-quality layout designs across analog and/or mixed-signal domains in collaboration with peer architecture, design, and packaging teams. Implement layout designs for early architecture concepts to demonstrate feasibility and identify optimizations. Responsibilities: Design layouts for critical analog and mixed-signal blocks. Drive exploratory layout process for next-generation architectures, including floorplanning, placement, and routing. Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation. Collaborate and communicate across domains, including signal integrity, architecture, design, and advanced packaging, to ensure successful architecture exploration. Minimum Qualifications: Hands-on layout experience with critical analog blocks and full designs. Experience with Cadence VLE/VXL and Mentor Graphics Calibre DR

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Power Delivery Network (PDN) Engineer , you will be part of the Heterogeneous Integration Group (HIG), responsible for the design, analysis, and optimization of power delivery networks for next-generation HBM products. You will work closely with architecture, design, physical design, packaging, and product engineering teams to ensure robust, efficient, and manufacturable power delivery solutions that meet aggressive performance, power integrity, and reliability targets. This is a hands-on technical role focused on PDN design, EM/IR analysis, and cross-domain optimization across technology, design, and layout. Key Responsibilities Design and develop SoC-level and HBM-cube-level power delivery networks for HBM designs, including power grid architecture, routing strategies, and decoupling schemes. Perform EM/IR analysis and optimization using industry-standard tools (e.g., Cadence RedHawk, Ansys Totem) to ensure power integrity across dynamic workloads. Collaborate with physical design teams on floorplanning, placement, and routing strategies to enable efficient PDN implementation. Drive power integrity closure across multi-mode/multi-corner scenarios, identifying and mitigating droop, noise, and electromigration risks. Work with package and system teams to co-optimize die-package-system PDN interactions, including bump/pad assignment and current distribution. Develop and validate power models, including activity-based current profiles and transient analysis for realistic

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: The Advanced Packaging Technology Development (APTD) team at Micron drives the technologies that enable the AI era. We work hands‑on with global R&D, suppliers, and manufacturing teams to turn breakthrough ideas into production‑ready solutions. Our work sits at the intersection of innovation, scale, and real‑world impact—and collaboration is how we win. Position Overview: Artificial intelligence is transforming the world, and High Bandwidth Memory (HBM) is at the center of that transformation. As a Senior or Staff Engineer on the Dry Etch R&D team, you will play a key role in developing and scaling plasma‑based etch processes that enable next‑generation packaging technologies. This role offers deep technical ownership, broad cross‑functional collaboration, and the opportunity to influence long‑term technology roadmaps from early research through high‑volume manufacturing. Responsibilities: Develop and optimize dry etch process modules to meet performance, yield, and reliability requirements for advanced packaging products Drive process capability, cost, and variability improvements using data‑driven experimentation and equipment innovation Collaborate closely with process integration and adjacent process teams including Wet Etch, Films, Lithography, CMP, Wafer Trim, and Bonding Perform root‑cause and failure‑mode analysis a