Physical Therapist Jobs

About Decagon Decagon is the leading conversational AI platform empowering every brand to deliver concierge customer experiences. Our technology enables industry-defining enterprises like Avis Budget Group, Block’s Cash App and Square, Chime, Oura Health, and Hunter Douglas to deploy AI agents that power personalized, deeply satisfying interactions across voice, chat, email, SMS, and every other channel. We’re building a future where customer experiences are being redefined from support tickets and hold music to faster resolutions, richer conversations, and deeper relationships. We’re proud to be backed by world-class investors who share that vision, including a16z, Accel, Bain Capital Ventures, Coatue, and Index Ventures, along with many others. We’re an in-office company, driven by a shared commitment to excellence and velocity. Our values — Just Get It Done, Invent What Customers Want, Winner’s Mindset, and The Polymath Principle — shape how we work and grow as a team. About the Team At Decagon, our offices are more than workplaces - they’re the center of how we build, collaborate and move fast together. From our San Francisco headquarters to expanding spaces in New York, Europe, Australia, and beyond, we create workplaces that are functional, inspiring and deeply aligned with Decagon’s culture. The Workplace team owns the strategy and operations behind our work environments, from real estate strategy and build-outs to the systems that keep our offices running seamlessly day to day. Our work directly shapes how Decagon operates, bringing intention and precision to the spaces where innovation happens. About the Role The Head of Real Estate & Workplace will own Decagon’s global real estate strategy, ensuring our physical environments scale in step with our growth. You will lead site selection, execute lease negotiations, and oversee new office buildouts. You will also lead the Workplace team that delivers an excellent employee experience in these offices day-to

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today, SpaceX is actively developing the technologies to make this possible, with the ultimate goal of making life multiplanetary and expanding consciousness to the stars. SpaceXSI is building Super Intelligence to help humanity understand the universe. Our teams are building the full Super Intelligence stack: from our Colossus supercomputers, to Grok models, to our suite of applications, including Grok Bot, Grok Build, Grok Imagine, Grok Voice, and X. We're creating a powerful flywheel where more compute trains better models, better models power more useful products, and what we learn from people using those products shapes what we build next. ABOUT THE ROLE: Join the High Power Engineering team supporting SpaceXSI to design, build, operate, and maintain electrical infrastructure for AI training campuses. As a Lead Engineer for Battery Storage, you will work with a small on-site team to scale high-capacity power systems on a schedule set by compute demand. The position is based in Memphis, TN, with potential travel to other sites. RESPONSIBILITIES: Own the storage fleet as a power plant, not as an accessory: architecture, sizing, controls, safety case, and grid-forming behavior that lets the campus ride through compute step loads and generation contingencies. Own BESS architecture: pack-to-MV-transformer grouping, string composition, medium-voltage collection topology, string-level protection, and physical block layout including spacing per NFPA 855. Own sizing; translate compute duty cycles — step loads, training-job ramps, actual-versus-nameplate utilization — into power and energy requirements. Own inverter control strategy: grid-forming versus grid-following, droop and virtual inertia, fault-current contribution, ride-through, and coordination with generation governors and excitation. Own the plant controller and

About the Team DoorDash is one of the world's most trusted on-demand logistics platforms. The Global Safety and Security team exists to keep it that way, protecting our people, property, operations, brand, and reputation across all our markets. We manage risk and create value through agility, technology, and a people-first approach. Our DoorDash, Deliveroo, and Wolt brands now span more than 40 countries, dozens of offices, and tens of thousands of employees. Protective Services is the function accountable for the safety of the people we protect and the environments they live and work in, wherever they are. About the Role We are hiring a Senior Manager, Protective Services to lead protective operations, reporting to the Director, Protective Services. This is as much a build-and-execute mandate as a leadership one. You own the decisions that keep protection working, including how teams are staffed and assigned, how protection is set for a given person and situation, what we spend and which vendors we use, what people are trained to do, and how incidents get handled. This is a player-coach role, and the coaching half does not keep you off the field. You will work advances, travel with the people we protect, and take your turn in the rotation while setting the standard the team works to. Protection here is a service. It works when the people we protect can move through their lives with as little friction as we can manage, and when they trust the team enough to tell us what we need to know. You own protective operations, training and standards, vendor management, incident response, and converged physical-cyber protection. Protective teams, intelligence, and cybersecurity work on the same problem simultaneously, and detection and intelligence capabilities drive our protective posture. Success in the first year means a tight operating rhythm, training and qualification standards that hold up against the best protective programs, a team that is current and deployable

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today, SpaceX is actively developing the technologies to make this possible, with the ultimate goal of making life multiplanetary and expanding consciousness to the stars. SpaceXSI is building Super Intelligence to help humanity understand the universe. Our teams are building the full Super Intelligence stack: from our Colossus supercomputers, to Grok models, to our suite of applications, including Grok Bot, Grok Build, Grok Imagine, Grok Voice, and X. We're creating a powerful flywheel where more compute trains better models, better models power more useful products, and what we learn from people using those products shapes what we build next. ABOUT THE ROLE: Join the High Power Engineering team supporting SpaceXSI to design, build, operate, and maintain electrical infrastructure for AI training campuses. As a Network Engineer on the Battery Storage team, you will work with a small on-site team to scale high-capacity power systems on a schedule set by compute demand. The position is based in Memphis, TN, with potential travel to other sites. RESPONSIBILITIES: Own the operational technology network the storage fleet runs on: packs, inverters, medium-voltage collection, and the plant controller must talk deterministically, redundantly, and securely. Own site network architecture: topology, redundancy, switch selection and configuration, VLAN and subnet design, and IP addressing across the fleet. Own the fiber and copper physical plant: single-mode and multimode runs, splice plans, patch panel layout, labeling, OTDR acceptance testing, and pathway coordination. Own industrial protocol integration across Modbus TCP, DNP3, and IEC 61850 including GOOSE, plus mapping between pack controllers, PCS, plant controller, and EMS. Own precision time distribution using PTP per IEEE 1588 and IRIG-B for sequence-of-events and disturb

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Develop and standardize EMIR methodology that applies consistently across all DRAM products, ensuring alignment, repeatability, and high-quality analysis outcomes Perform static and dynamic EM/IR and PDN analysis using RedHawk or Totem or other industry‑standard tools; identify root‑cause issues such as high‑resistance segments, insufficient via density, and decap deficiencies, and provide clear, actionable recommendations to design and layout teams. Actively leverage AI‑based tools, agentic workflows, and automation frameworks for effective Power-delivery-network (PDN) analysis. Maintain a strong understanding of the full EMIR flow—from netlist preparation, extraction, simulation, and debug to reporting and silicon correlation—and ensure accurate evaluation across operating modes and temperatures. Partner across design, timing, physical implementation, architecture, modeling, and verification teams to understand real switching behavior, develop worst‑case vectors, and standardize analysis expectations across global teams. Collaborate with cross-geographical teams and also EDA tool vendors to evaluate and improve EMIR methodologies, and document Best Known Methods (BKMs) to enhance consistency and correlation across DRAM teams. Develop and maintain dashboards to track EMIR results, monitor trends, and support signoff progression for multiple designs. Qualifications: Master’s degree i

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Senior Engineer, MCT Operations Quality at Micron Technology, Inc., you will lead and collaborate closely with Global Assembly & Test (AT) sites, Global Quality, and various cross-functional stakeholders to drive on Manual Touchpoint Reduction. You will champion a Quality-First mindset by driving manufacturing solutions and end-to-end redesign initiatives to eliminate manual steps upfront that reduce operational error, prevent customer events and enhance product quality across Global AT network. Job Responsibilities: Lead global initiatives and collaborate with AT sites and Global Quality to identify and eliminate high-risk manual touchpoints across Assembly, Test/Post E, Module/SSD, HBM/PWF areas. Conduct onsite validation of the manual touchpoints at the source, identify quality risks, and propose improvements to eliminate the touchpoints. Collaborate with subject matter experts and drive the development and deployment of scalable solutions through physical automation/robotics, system automation, and Predictive Quality & Generative AI-enabled solutions. Collaborate with subject matter experts on end-to-end redesign initiatives to eliminate manual touchpoints upfront. Lead as the central team program governance to drive strategy, alignment, and execution consistency across all AT sites. Drive the rapid replication and scaling of proven solutions across AT sites through struct

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role The Corporate Network Engineering team owns Anthropic's corporate network: the wired, wireless, and edge infrastructure in our offices and research facilities around the world, and the standards, management systems, and telemetry that let a small team run them. We hold that network to the bar of a production service — designed for failure, managed as code, observable end-to-end, and secure by default — while delivering reliable connectivity to the people who depend on it every day. You'll set the technical direction together with your engineers and own the final decision on it and on the architecture standards, review and guide designs and the hard trade-offs, and lead vendor and platform decisions. You'll lead and grow a small team of network engineers: set priorities, drive decisions to closure, hire, and develop people. The team is small and the scope is broad, so this role needs real depth in campus and edge networking, judgment about what to standardize, automate, buy, and build, and the range to go from a wiring-closet decision to a budget defense in the same afternoon. You'll report to the head of IT Engineering and partner closely with our Buildouts, AV, and Endpoint teams; with Security Engineering on network security, authentication, and detections; with Physical Security, whose systems are critical for protecting Anthropic employees and depend on a reliable network; with Workplace, Real Estate, Procurement, and external logistics and integration partners on new site buildouts; and with our production networking teams, whose bar for reliability and automation is the one we hold ourselves to. Your work will dir

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Lead DFT Engineer Job Description: Developing silicon for edge-to-cloud computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities: Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST. Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis . Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time. Technical Requirements: Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Bachelor’s degree in a related field. Tools:

JOIN OUR TEAM As a Product Manager Westwing Collection , you will shape and drive the assortment strategy for your assigned product categories, owning the end-to-end product lifecycle from strategic planning to portfolio optimisation and commercial performance. You will define and execute category strategies, identify growth opportunities, and continuously evolve the assortment to strengthen the positioning of the Westwing Collection. Through active portfolio management and close collaboration with Design, Buying, and key stakeholders, you will ensure a relevant, inspiring, and commercially successful portfolio offering. This position is permanent and based in Munich . WHAT YOU'LL DO Develop and execute best-in-class assortment strategies by analysing the market and identifying key growth opportunities for the Westwing Collection Build a unique and inspiring product portfolio for the Westwing Collection in close alignment with the Design and Buying teams Maintain a healthy port folio through active portfolio management, bringing a proactive and entrepreneurial attitude Identify sales, merchandising, and operational opportunities, leveraging AI tools and automation to optimise commercial performance Partner closely with cross-functional stakeholders, including Buying, Design, Supply Chain, Product Quality, and Onsite Merchandising, to drive seamless execution YOU COME WITH 5+ years of experience in physical product management, consumer retail, or business development Strong commercial acumen and analytical problem-solving skills with a bias for fast execution A proactive, ownership-driven mindset with the ability to work independently in a fast-paced environment Deep passion for interior design and home & living, with an intuitive product sense Clear, persuasive communication and stakeholder management skills across cross-functional teams Fluency in English; additional European languages are a plus WHY WESTWING If you are looking for a place where ambition meets crea

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. About the Role We’re looking for a Sales Solution Engineer in Vietnam to work with enterprise customers, system integrators, MSPs, and channel partners. You’ll design and present end-to-end solutions across networking, ProAV, VoIP, storage, and Physical Security (Protect & Access). As a key solution engineering lead in Vietnam, you’ll play an important role in market expansion. Working in a pre-sales capacity, you will help lead regional technical strategy for Ubiquiti in Vietnam, collaborating with product teams, partners, and global sales to drive adoption, market fit, and brand growth. Responsibilities Design scalable solutions across Network, Protect, Talk, Drive, and Access Deliver demos, POCs, webinars, and technical workshops Build proposals, architectures, and BoMs Enable partners and distributors Drive product visibility in retail and online channels Share market feedback with global teams Desired Experience Solution Architecture Enterprise Networking (SD-WAN, MC-LAG, BGP, OSPF) ProAV (AV-over-IP, PTP) Physical Security (CCTV & Access Control) VoIP (SIP, PBX systems) Storage (NAS, SAN) General Native Vietnamese and business English 3+ years in pre-sales, solution engineering, or system design Certifications (CCNP, CWNP, UWA) preferred Strong reliance on AI tools, LLMs, and automation to drive productivity and sca

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Life at Intel We developed the Intel E-Core microprocessors, a foundational technology that powers a diverse range of devices-from entry-level PCs to high-end gaming desktops and laptops, as well as data center solutions and many other applications. As part of our team, you will help design the next generation of high-performance microprocessors. We are looking for a skilled individual who has hands-on experience in RTL methodologies, coding, debug and effective use of AI tools and can provide technical leadership to deliver world-class products. As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to: Demonstrated leadership and hands-on experience in leveraging AI tools and methodologies to drive significant efficiency gains and improvements in RTL coding and other areas of silicon development. Proactively advances front-end methodologies and contributes to architectural and microarchitectural discussions to enhance scalability and flexibility. Develops and implements strategies, tools, and techniques for RTL development and logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as physical design integrity.

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Life at Intel We developed the Intel microprocessors, a foundational technology that powers a diverse range of devices-from entry-level PCs to high-end gaming desktops and laptops, as well as data center solutions and many other applications. As part of our team, you will help design the next generation of high-performance microprocessors. We are looking for a skilled individual who is hands-on with RTL implementation for integer, floating point and reservation station logic and can provide technical leadership to deliver world-class products. As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: • Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. • Participates actively in the definition of architecture and microarchitecture features of the CPU being designed. • Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. • Reviews the verification plan an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, the Process Pathfinding organization develops next-generation semiconductor memory technologies and innovative device architectures. The team focuses on advancing process technologies that enable future memory products through fundamental research, process integration, and collaboration across engineering fields. This is an outstanding opportunity to contribute to innovative semiconductor development in a fast-paced, knowledge-focused environment. As a DRAM Dry Etch Process Pathfinding Intern, you will support the development of advanced plasma etch processes for emerging memory technologies. Working alongside experienced engineers and multi-functional partners, you will gain hands-on experience with dry etch equipment, semiconductor process development, materials characterization, and data-driven problem solving. This role provides exposure to advanced manufacturing environments while contributing to process solutions that improve device performance and reliability. Responsibilities Conduct experiments and fundamental research to develop innovative dry etch solutions for next-generation memory technologies. Partner with the Pathfinding team to develop and optimize dry etch processes that meet physical and electrical performance requirements. Apply analytical, statistical, and problem-solving methods to evaluate process performance, hardware capability, and process capability, and aid in