Senior Silicon Validation Methodology Engineer Jobs

About Graphcore Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Join our dynamic Software Infrastructure team and take a pivotal role in scaling and managing our infrastructure. You will develop essential tools and services that empower our broader software team. Your contributions will enhance the build, test, deployment, and productisation processes of our Machine Learning Software components. Work with our High-Performance Computing (HPC) AI platforms and gain invaluable experience in distributed systems. The Team The Software Infrastructure team provides critical platforms and services for software development teams across the business. Our responsibilities include managing the CI platform and services, build engineering, component integration, and packaging and release systems. We operate in squads, fostering a culture of service ownership and empowerment for our engineers. We focus on long-term engineering solutions and strive to eliminate toil wherever possible. Responsibilities and Duties Develop, own, and maintain tools and services to support the software build and release process Deploy and maintain services with Kub

Since 2003, Entrata has evolved from a visionary, student-led startup into a global leader in AI-driven property management technology. Today, we power the industry's most essential operating system, serving owners and residents worldwide through a comprehensive suite of intelligent leasing, payment, and communication tools powered by cutting-edge AI. With a proven track record of sustained growth and a global team of more than 2,200 employees, we offer the rare combination of established stability and high-velocity innovation. Recognized by the Silicon Slopes Hall of Fame and the Utah Business Fast 50, Entrata fosters a culture of radical transparency and entrepreneurial energy. At Entrata, we create an environment where different perspectives are valued and respected. Those perspectives challenge assumptions, strengthen our decisions, and raise the bar as we reshape the global living experience through AI-powered solutions. We are seeking a Senior Machine Learning Engineer to help build and scale Entrata’s applied AI capabilities. This role will focus on adapting and fine-tuning foundation models for property management use cases, building reliable model training and evaluation pipelines, and deploying AI systems into production.

Since 2003, Entrata has evolved from a visionary, student-led startup into a global leader in AI-driven property management technology. Today, we power the industry's most essential operating system, serving owners and residents worldwide through a comprehensive suite of intelligent leasing, payment, and communication tools powered by cutting-edge AI. With a proven track record of sustained growth and a global team of more than 2,200 employees, we offer the rare combination of established stability and high-velocity innovation. Recognized by the Silicon Slopes Hall of Fame and the Utah Business Fast 50, Entrata fosters a culture of radical transparency and entrepreneurial energy. At Entrata, we create an environment where different perspectives are valued and respected. Those perspectives challenge assumptions, strengthen our decisions, and raise the bar as we reshape the global living experience through AI-powered solutions. We are seeking a Senior Data Scientist to help improve the quality and performance of Entrata’s AI models and applications. This role will focus on fine-tuning strategy, training data, experimentation, evaluation, and identifying the approaches that produce the best outcomes for complex property management workflows.

Job Details: Job Description: About the Role Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies. What You’ll Do Key responsibilities will include but not limited to: Own physical design and implementation of CPU core blocks or subsystems Execute synthesis, floorplanning, place and route, and design closure Perform static timing analysis (STA), power analysis, and physical verification Drive convergence of timing, power, and area (PPA) metrics Debug and resolve complex design issues across multiple design stages Develop and optimize design flows and automation scripts Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams Contribute to improving design methodologies and best practices Provide guidance to junior engineers where applicable Behavioral traits that we are looking for: Strong problem-solving and analytical thinking Takes ownership and accountability for deliverables Collaborates effectively across multidisciplinary teams Communicates technical concepts clearly and concisely Prioritizes work effectively in a fast-paced environment Continuously learns and applies new tools and methodologies Why Join Us Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide Be part of

We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading GPU and SoC's. With the System-ASIC team, you will contribute to designing multiple products that will be used in a variety of applications from consumer graphics to self-driving cars and the growing field of artificial intelligence. System-ASIC team works closely with System Architecture team on product definitions, implements new innovative flows to improve our chip yield and to address multiple sectors, defines Reset and Boot Architecture and implements them in complex GPU and Tegra chips. The team is also handling the architecture, design, and synthesis of multiple System-level modules. What you’ll be doing: Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs Collaborate with architects, ASIC designers, and verification engineers to design sophisticated system-level modules such as Floorsweep, In-silicon measurement, Reset and Boot controllers. You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. Integrate modules into the overall SOC design and work closely with other teams in the silicon bring-up process and ensure successful SOC le

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Summary: We are seeking an experienced Fail-Mode Metric Reaction (FMR) Engineer to drive yield analysis, failure mode characterization, and failure mechanisms understanding across test vehicles and advanced packaging products. This role owns the reaction loop between defect signatures observed in the line and the corrective actions taken by process, build, and reliability partners — spanning time-zero defects, internal reliability fails, and customer RMA returns! Job Description: Key Responsibilities: Perform yield analysis for advanced packaging test vehicles and production products, producing clear breakdowns of defect signatures by fail mode, location, layer, and process step. Investigate and root-cause fail modes and fail mechanisms at time-zero, correlating electrical signatures with physical failure analysis findings. Drive reaction plans on internal reliability fails and customer RMAs, translating failure mechanism understanding into containment, corrective, and preventive actions. Partner closely with: APTD Process teams — for process excursion triage and corrective action. APTD FA labs — for physical FA planning, sample prioritization, and interpretation. PSE (Product/Package Silicon Engineering) and TSE (Test/Silicon Engineering) teams — for test coverage, screen enhancement, and product-level dispositioning. Build and maintain data analysis pipelines, dashboards, and automated wor

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas. This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs. Partner with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips. You will work on post-silicon data analysis for power to architect the next-gen solutions. In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions. Help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equivalent experience) with 12+, MSEE with 10+, or PhD with 6+ years of experience in DFT design & power

NVIDIA is looking for a Senior ASIC Verification Engineer to help verify our global IP! This position offers an opportunity to impact an array of products while collaborating with teams from design, architecture, verification, and integration. At NVIDIA, we have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will partner with the design and architecture teams to help make the right implementation choices, craft and implement verification test plans, maintain regressions, close coverage and sign off design or both functional correctness and for meeting performance expectations. This position offers the opportunity to have a real impact on multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI! What you'll be doing: Develop test plans, tests and verification infrastructure for verifying global IP across multiple products Define, develop, and automate flows and methodologies to efficiently build, deploy, and verify generated RTL Ensure code and functional coverage of all the RTL which you will verify Build verification components using SV/UVM methodology Driving coverage-based verification closure Collaborate with design teams across NVIDIA to find corner cases and resolve verification related issues What we need to see: BS/MS in Electrical or Computer Engineering (or equivalent experience) 5+ years of proven design verification experience Experience in pre-silicon verification (UVM, SystemVerilog), ASIC design/implementation flow, and design automation Programming and scripting experience in Perl or Python Excellent debugging and analy

About the job Own the manufacturing performance behind advanced AI compute systems in volume production. As, Senior Manufacturing Product Engineer you will connect product design, test, quality and supply chain with manufacturing execution. You will support volume production across PCB assembly with our build partners in Taiwan. Your work will improve yield, quality and manufacturability across complex products. You will link manufacturing process performance to the product metrics that matter most. You will manage partner engineering relationships, resolve manufacturing issues and drive continuous improvement. You will also shape DfM feedback, production data requirements and next generation manufacturing technologies. This role suits someone who combines practical manufacturing judgement with strong data thinking. You will work close to suppliers, product teams and the decisions that shape production outcomes. The team and culture You will join the Manufacturing and Technology Process team within Operations. The team works across Bristol, Cambridge and Taiwan, close to wafer foundry, package assembly and PCBA subcontractors. Work happens through direct ownership at partner sites and clear technical engagement with internal teams. You will move quickly on production issues, using data and engineering judgement to guide action. The team values people who speak up, take responsibility and build strong supplier relationships. Decisions are grounded in evidence, product impact and the need to keep manufacturing improving. What we're looking for · Strong fault diagnosis, problem solving and failure analysis skills, including ICT to SMT debug · Thorough understanding of automated SMT assembly processes and lean manufacturing methodologies · Working knowledge of L10 mechanical design and system build, ideally for HPC products · Experienced in statistical analysis tools (e.g JMP, SQL, Python) · Ability to connect silicon, package and PCB interactions into clear DfM

NVIDIA is seeking a Senior Technical Program Manager to join the CSP Engagements team, focused on deep technical engagement with hyperscale cloud service providers for NVIDIA’s next‑generation datacenter systems such as Vera Rubin NVL72. This role is intended for experienced systems and embedded software leaders—including software engineering managers, technical leads, or senior architects—who have led datacenter server and platform software programs and can operate as a trusted technical partner to hyperscale CSP engineering teams. As a member of the CSP Engagements team, you will act as the primary technical engagement leader between NVIDIA’s system software organizations and CSP platform, system software, and AI teams, ensuring alignment, readiness, and successful large‑scale deployment of NVIDIA‑based datacenter solutions. What you will be doing: Lead deep technical engagements with hyperscale CSPs as the primary NVIDIA point of contact for system software, firmware, and platform readiness for NVIDIA datacenter products. Partner directly with CSP system software, firmware, and infrastructure engineering leaders to align on software architecture, bring‑up plans, deployment readiness, and production requirements for NVIDIA‑based server and rack‑scale platforms. Represent CSP technical priorities internally, advocating for customer requirements and tradeoffs across NVIDIA’s system software, firmware, hardware, silicon, and product teams are aligned to customer needs, timelines, and constraints. Own the end‑to‑end CSP engagement lifecycle, from early technical alignment and pre‑production readiness through large‑scale deployment, escalation management, and sustained production support. Drive bi‑directional technical communication: translating CSP system‑level requirements into actionable focus areas for NVIDIA engineering teams, while clearly communicating N

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s Heterogeneous Integration Group (HIG) is shaping the future of AI and accelerated computing by developing advanced memory solutions! The team focuses on designing and optimizing High Bandwidth Memory (HBM) products for AI/ML, high-performance computing (HPC), and data-centric systems, collaborating across global engineering and product teams to deliver industry-leading performance, power efficiency, and reliability! HBM product family is growing due to high demand from industry-leading semiconductor companies. As an HBM Memory Design Engineer you will work closely with cross-functional teams including Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging, and Technology Development (TD) to analyze and resolve silicon issues across HBM products . You will collaborate with architecture to understand new or updated specification requirements and contribute to the implementation, verification, and maintenance of design updates , supporting both silicon release and ongoing product lifecycle needs. This role requires strong AI driven technical execution and the ability to independently drive complex issues to closure. Responsibilities Design Support: Work on HBM product design and support sustaining design maintenance (ECOs/spec changes). Silicon Debug: Own end-to-end debug of silicon, system, and customer issues, driving root-cause analysis and resolution. Cross-Functional Collaboration: Work closely with DE, PE, TD,

Job Details: Job Description: Shape the Future of Semiconductor Manufacturing at Intel Join Intel's newest and most innovative organization—Manufacturing Development Customer Engineering (MDCE)—where you'll bridge the critical gap between breakthrough technology development and high-volume manufacturing. As a Senior Wet Etch Manufacturing Development Engineer, you'll be at the forefront of advancing next-generation semiconductor technologies that power the world's most sophisticated devices. Organization Impact MDCE represents Intel's strategic evolution within Intel Foundry Technology Manufacturing (FTM). We're the vital link that transforms cutting-edge research into manufacturable reality, advancing technology nodes from initial qualification to high-yield production while delivering enhanced solutions for foundry customers worldwide. Your Role in Technology Leadership Drive technology innovation that defines Intel's future roadmap while enabling advanced manufacturing processes that set industry standards. You'll develop next-generation device architectures, support high-volume production scaling, and collaborate with world-class suppliers to deliver breakthrough solutions that maintain Intel's semiconductor leadership. Direct Impact Your innovations will power billions of devices globally, ensuring Intel's continued dominance in delivering world-class silicon solutions that push the boundaries of what's technologically possible. Core Responsibilities Advanced Process Development Lead design, development, and optimization of sophisticated manufacturing processes Drive parameter optimization, material selection, and system design to exceed functional requirements

Job Details: Job Description: The Role and Impact We are seeking a Silicon Packaging Design Architect to join our team, where you will drive end-to-end package solutions for physical, electrical, and cost requirements. In this senior engineering role, you will collaborate with cross-functional teams to design, troubleshoot, and continuously improve packaging standards and processes, ensuring high-quality package output. Your contributions will directly impact the seamless transition of designs to production and enhance Intel's advanced packaging technologies. Business Group As part of Intel Corporation's dynamic and innovative ecosystem, this role resides within the Silicon Packaging Architecture team, focused on developing advanced packaging solutions that enable Intel's cutting-edge silicon technologies. The team plays a vital role in ensuring packaging, and 3D IC designs meet technical, mechanical, and reliability standards while supporting Intel's broader mission to drive world-changing advancements in technology. Key Responsibilities Translate product requirements into detailed package architecture specifications. Drive technology tradeoff decisions to ensure silicon packages conform to electrical, mechanical, thermal, and reliability standards. Collaborate with silicon, hardware, and package teams to deliver high-quality package solutions and overcome roadblocks. Oversee the end-to-end package development process, including design, procedures, and continuous improvements to quality standards. Troubleshoot packaging designs and resolve issues related to materials and processes, providing innovative and cost-effective solutions. Implement co-design strategies between silicon and board design teams to optimize product

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In the Technology - Advanced Modeling and AI Solutions (AMAIS) Group in Hyderabad, you will work in a multi-functional team of engineers highly skilled in the modeling of process, equipment, structures, and materials. This team’s primary responsibility is to support and enable solutions to Micron’s most significant challenges in Memory development and manufacturing. Your role will be to work on a project that directly supports one of our group’s critical programs. This project will involve materials or structure or process modeling. You are expected to work in a dynamic and fast-paced team environment developing models and reporting results to the AMAIS team and collaborating with them on next steps. This position seeks individuals that can code, implement, and utilize numerical models. You will interact with process engineers and development teams to identify questions and issues hindering the node development milestones. Additionally, you will create software programs, algorithms, and computational modeling tools to extract concrete insights from modeling and data. You will interpret and convey these insights and findings from models and experiments to engineering teams and leaders. You will be responsible for predictive structure modeling across multiple DRAM and NAND nodes. The modeling engineer will collaborate extensively with product design and process teams for structure model development, deployment, and providing solutions to be implemented on Silicon. Qualifica

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s Heterogeneous Integration Group (HIG) is shaping the future of AI and accelerated computing by developing advanced memory solutions! The team focuses on designing and optimizing High Bandwidth Memory (HBM) products for AI/ML, high-performance computing (HPC), and data-centric systems, collaborating across global engineering and product teams to deliver industry-leading performance, power efficiency, and reliability! HBM product family is growing due to high demand from industry-leading semiconductor companies. As an HBM Design Engineer, you will work closely with cross-functional teams including Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging, and Technology Development (TD) to analyze and resolve silicon issues across HBM products . You will collaborate with architecture to understand new or updated specification requirements and contribute to the implementation, verification, and maintenance of design updates , supporting both silicon release and ongoing product lifecycle needs. This role requires strong technical execution and the ability to independently drive complex issues to closure. Responsibilities Design Support: Work on HBM product design and support sustaining design maintenance (ECOs/spec changes). Silicon Debug: Own end-to-end debug of silicon, system, and customer issues, driving root-cause analysis and resolution. Cross-Functional Collaboration: Work closely with DE, PE, TD, and system teams