Senior Silicon Validation Methodology Engineer Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Job title Senior DFT Engineer Job description We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. Your responsibilities Integrate and verify test features in digital designs for effective manufacturing testing and silicon debug. Key responsibilities include: Building entire chip-level DFT strategies Inserting DFTs, including scan chains, memory BIST, and JTAG Collaborating with RTL, physical design, and verification teams for testability throughout the design flow Scripting and automating DFT flows using industry-standard EDA tools (e.g., Cadence, Synopsys, Siemens) Running and analyzing ATPG and fault coverage reports Supporting silicon bring-up and debug related to test features Knowledge of advanced silicon technologies and methodologies for test coverage optimization Experience with formal verification and signoff of inserted DFT logic Strong communication and collaboration skills for cross-functional teamwork Exp

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas. This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs. You will work with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips. You will work on post-silicon data analysis for power to architect the next-gen solutions. In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions. You will also help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equ

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Unique Opportunities Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 9600MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on multi-functional tasks that can widen your skill set and experience in managing design verification of large and complex design Responsibilities Guide and set the broader direction for the verification effort of any project that the team undertakes. Lead cross-site efforts in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Provide advice to senior management on significant technical issues. Strive to establish best known methods (BKM) within the group by driving development meetings, technical forums, etc. Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Drive development of test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements using Agentic AI</spa

About the Role We’re seeking an Associate General Counsel to lead commercial legal strategy and execution for OpenAI’s silicon initiatives and the semiconductor ecosystem that supports our AI infrastructure. This is a senior, highly cross-functional role for a lawyer who can advise business and technical leaders across the semiconductor development, manufacturing, and supply lifecycle. The role will partner closely with silicon engineering, infrastructure, strategic sourcing, supply chain, manufacturing, finance, partnerships, IP, policy, regulatory, and trade compliance teams to structure and negotiate strategic arrangements with semiconductor ecosystem partners, technology providers, and critical suppliers. This person will help establish the commercial frameworks needed to protect OpenAI’s technology and support resilient, scalable commercial arrangements. We’re looking for an experienced technology transactions lawyer with meaningful semiconductor industry experience who can translate highly technical and operational issues into practical commercial structures. The ideal candidate combines strong judgment, commercial creativity, and the ability to lead complex, high-value transactions in a fast-moving and complex global ecosystem. This role is based in San Francisco, CA. We use a hybrid work model of 3-days in the office per week and offer relocation assistance to new employees. This role will: Lead commercial legal strategy and risk management for OpenAI’s silicon and related technology initiatives. Advise senior business, engineering, sourcing, and operational stakeholders on strategic relationships, commercial priorities, and complex transactions. Draft, negotiate, and advise on sophisticated development, manufacturing, supply, licensing, services, and strategic partnership agreements. Structure commercial arrangements that support long-term business and operational requirements. Advise on the commercial and operational issues that arise across the developmen

About Graphcore At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. The Team The Verification team sits within the Silicon Design organisation. We ensure that the RTL delivered by Logical Design and used by Physical Design team implements Graphcore’s architectural needs and meets the company's quality standards. As a Director of Silicon Verification, you will help lead this multi-site organisation, define verification strategies across multiple silicon programs, and drive best in class execution to ensure high-quality, high-performance silicon delivery. Role Summary We are seeking a proven leader to help direct Graphcore’s verification strategy and methodologies. This role sets direction for the verification lifecycle including - planning, infrastructure, execution, coverage closure, debug strategy and sign-off for Graphcore’s complex, high performance AI accelerators. Reporting to the Senior Director of Verification the Director will partner closely with other teams such as Architecture, Logical Design, Physical Design, DFT, Systems as well as Program Management teams to ensure accurate implementation, accelerated debug cycles, high coverage confidence and predictable silicon delivery. Responsibilities Leadership & Strategy Define t

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a senior engineer to improve the reliability, performance, and user experience of the high-performance computing infrastructure that supports silicon development. This role sits at the intersection of EDA, distributed systems, CI/CD, and developer productivity. You will help engineering teams run simulations, verification, coverage, and other silicon-development workloads with fewer failures, shorter feedback cycles, and better operational visibility. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Hold an advanced engineering degree (BS, MS, or PhD in EE, ECE, CS, or related field) paired with over seven years of hands-on industry experience. Bring expertise in Git branch strategies, merge conflict resolution, operational failure debugging, and software engineering repository management practices. Possess practical working knowledge of SQL databases, data query optimization, and modern structured data technologies. Leverage AI-assisted development tools and agentic workflows to solve complex technical problems, enhance automated testing, and streamline

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a SoC Architecture and Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the architecture, design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, design, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. This is a hands-on technical role for candidates passionate about architecture, RTL build, IP integration, debugging, and pre/post-silicon support. Key Responsibilities Architect, design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Architect and design memory sub-systems including memory IP selection and integration, bus and protocol selection, and power/performance/area optimization. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Trans

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a senior High Speed Interconnect / Signal Integrity Engineer to design and validate high-bandwidth links for large-scale AI systems. You will define, model, and qualify interconnect solutions across copper and optical technologies for next-generation AI inference and training clusters. This role is on-site in Santa Clara, CA, Austin, TX, or Toronto, Canada. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are An experienced electrical engineer with a Bachelor’s or Master’s in Electrical Engineering. 5+ years working on high-speed communications (100G–1.6T), including signal integrity, channels, and links. Comfortable building and owning link and channel budgets and making clear tradeoffs between reach, loss, BER, and margin. Hands-on with SI tools and lab equipment such as Keysight ADS, VNAs, TDRs, BERTs, and protocol analyzers. Familiar with cable specification and testing, as well as accelerated life testing, mating life, and failure analysis. Able to collaborate across hardware, systems, and manufacturing teams; manufacturing/DFM/DTM experience is a plus. What We Need Define and specify high-speed interconnect architectures

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The DRAM IP Development (IPDEV) team develops critical digital IP solutions that enable next-generation AI, mobile, client, data center, and graphics memory products. Our team is responsible for delivering high-quality DRAM IPs that drive innovation, product performance, and development efficiency across Micron's memory portfolio. As a Senior or Graduate Engineering Intern in DRAM Circuit Design, you will work alongside experienced engineers to develop and validate digital IP circuits used in future DRAM products. This internship provides hands-on experience with RTL-to-GDS design methodologies, custom design and verification flows, silicon learning, and advanced semiconductor development processes. You will contribute to impactful engineering projects while gaining exposure to industry-standard EDA tools, multi-functional collaboration, and AI-enabled engineering workflows. Responsibilities Support the design, development, and verification of digital IP circuits for next-generation DRAM products using RTL-to-GDS methodologies. Perform circuit analysis across process, voltage, and temperature (PVT) corners to evaluate performance, quality, and reliability. Develop automation scripts and leverage Agentic AI, AI-Assisted tools, or Code Assist solutions to improve engineering productivity and design quality. Collaborate with multi-functional engineering teams on design implementation, verification,

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics. This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners. In this role, you will: Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic. Design mechanisms for routing, arbitration, ordering, flow con

About Ema Ema builds AI Employees for HR, IT and Finance. Our AI Employees take on the busy work across the employee experience, from recruiting, onboarding and benefits to IT support, invoice processing and payroll, so people can spend their time on work that needs them. Founded by former executives from Google, Coinbase, Flipkart, and Okta, our team includes engineers from premier tech companies and graduates of Stanford, MIT, UC Berkeley, CMU, and IITs. We are backed by industry leading investors including Accel, Naspers/Prosus, Creaegis, Section32, and angels like Sheryl Sandberg and Dustin Moskovitz. Headquartered in Silicon Valley and with offices in London, Bangalore and Vancouver, Ema is at the frontier of what Agentic AI can do in production. We ship real systems that run real business processes at scale. Role Overview & Key Responsibilities This is a high-leverage leadership role that spans architecture, execution, and org-building, and will shape the direction of our AI / ML initiatives at Ema. We are seeking an AI / ML technical leader who can take a vision and build it. As a Principal ML Engineer at Ema, you will be a senior technical leader responsible for shaping the machine learning roadmap, architecting large-scale ML systems, driving innovation, and ensuring our mixture of expert models (LLM + SLM + Custom Model) is accurate and performant at scale. You will collaborate across teams (research, product, infra, data, etc.), mentor senior engineers, and influence strategy and execution at company-wide levels. Responsibilities Lead the technical direction of GenAI and agentic ML systems that power enterprise-grade AI agents — spanning reasoning, retrieval, tool use, and integrations across various SaaS products. Architect, design, and implement scalable production pipelines for model training, fine-tuning, retrieval (RAG), agent orchestration, and evaluation — ensuring robustness, latency efficiency, and continuous learning. Define and own the mult

About Ema Ema builds AI Employees for HR, IT and Finance. Our AI Employees take on the busy work across the employee experience, from recruiting, onboarding and benefits to IT support, invoice processing and payroll, so people can spend their time on work that needs them. Founded by former executives from Google, Coinbase, Flipkart, and Okta, our team includes engineers from premier tech companies and graduates of Stanford, MIT, UC Berkeley, CMU, and IITs. We are backed by industry leading investors including Accel, Naspers/Prosus, Creaegis, Section32, and angels like Sheryl Sandberg and Dustin Moskovitz. Headquartered in Silicon Valley and with offices in London, Bangalore and Vancouver, Ema is at the frontier of what Agentic AI can do in production. We ship real systems that run real business processes at scale. The Role We are hiring an experienced Enterprise Business Development Representative (BDR) to own strategic account development and generate high-quality sales qualified leads (SQLs) with senior enterprise stakeholders. This is a high-impact, outbound-focused role built for someone who knows how to break into complex accounts, build credibility with executives, and create a real pipeline — not just activity. You will operate at the center of Ema's go-to-market motion, partnering closely with Sales and Marketing to build repeatable enterprise pipeline generation. What You'll Do Own outbound prospecting including defining your set of target enterprise accounts Identify, engage, and qualify Directors, VPs, and C-level decision-makers at $1B+ revenue organizations Develop account entry strategies and multi-thread across buying committees Drive prospects from cold outreach through qualification to booked SQLs using multiple channels (email, cold calls, LinkedIn) Partner with Account Executives to ensure strong handoff and pipeline conversion Own your book of business — know your metrics, your pipeline value, and your assigned solutions Contribute to outbound pl

About Ema Ema builds AI Employees for HR, IT and Finance. Our AI Employees take on the busy work across the employee experience, from recruiting, onboarding and benefits to IT support, invoice processing and payroll, so people can spend their time on work that needs them. Founded by former executives from Google, Coinbase, Flipkart, and Okta, our team includes engineers from premier tech companies and graduates of Stanford, MIT, UC Berkeley, CMU, and IITs. We are backed by industry leading investors including Accel, Naspers/Prosus, Creaegis, Section32, and angels like Sheryl Sandberg and Dustin Moskovitz. Headquartered in Silicon Valley and with offices in London, Bangalore and Vancouver, Ema is at the frontier of what Agentic AI can do in production. We ship real systems that run real business processes at scale. The Role We are hiring an experienced Enterprise Business Development Representative (BDR) to own strategic account development and generate high-quality sales qualified leads (SQLs) with senior enterprise stakeholders. This is a high-impact, outbound-focused role built for someone who knows how to break into complex accounts, build credibility with executives, and create a real pipeline — not just activity. You will operate at the center of Ema's go-to-market motion, partnering closely with Sales and Marketing to build repeatable enterprise pipeline generation. This role supports the US market and requires working US business hours. What You'll Do Own outbound prospecting including defining your set of target enterprise accounts Identify, engage, and qualify Directors, VPs, and C-level decision-makers at $1B+ revenue organizations Develop account entry strategies and multi-thread across buying committees Drive prospects from cold outreach through qualification to booked SQLs using multiple channels (email, cold calls, LinkedIn) Partner with Account Executives to ensure strong handoff and pipeline conversion Own your book of business — know your metrics, y

About the Team OpenAI’s Legal team plays a crucial role in advancing our mission by tackling novel and consequential legal issues in AI. The commercial infrastructure legal team supports the systems and facilities that make advanced AI possible, including compute, first-party silicon, colocation, and first-party data center development. About the Role We’re seeking a senior commercial infrastructure lawyer to lead legal work across our rapidly growing data center development and colocation portfolio. You will advise on complex, high-value transactions involving new data center sites, power, construction, colocation, and related infrastructure arrangements. This role is designed for a lawyer who understands how data centers are developed and operated—not a general real estate practitioner. You will work closely with infrastructure, finance, procurement, and operations teams, while coordinating outside counsel where appropriate, to help projects move quickly and responsibly. San Francisco is preferred, and occasional travel may be required. In this role, you will: Lead commercial legal strategy and risk management for data center development and colocation transactions. Draft, negotiate, and advise on colocation agreements, construction agreements, power-related arrangements, and other contracts supporting data center development. Support first-party projects involving raw land, site and power rights, design and construction, EPC models, third-party build-to-suit structures, and leasebacks. Partner cross-functionally with infrastructure, finance, procurement, operations, and other stakeholders on fast-moving, complex projects. Manage and collaborate effectively with outside counsel across a high volume of infrastructure matters. Develop scalable legal playbooks and contracting approaches for a growing portfolio of data center sites. You might thrive in this role if you have: 12+ years of legal experience, primarily in commercial legal roles. Deep, hands-on experience

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop DRAM digital and mixed-signal blocks for advanced memory products. In this role, you will support the RTL lifecycle from specification and implementation to signoff. You will collaborate with multi-functional teams to develop high-quality builds that meet power, performance, and area (PPA) targets. This position is based in Boise, Idaho, within a collaborative and innovative engineering environment. Responsibilities Contribute to RTL build of digital and mixed-signal components for DRAM using RTL-to-GDS flows. Implement and document high-performance, power- and area-efficient RTL designs meeting product specifications. Perform front-end quality checks including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design and implementation teams to achieve timing closure and PPA goals. Apply power-, clock-, and implementation-aware RTL design practices to minimize silicon risk. Minimum Qualifications Master’s degree in Electrical Engineering with 4&#43; years of experience, or Bachelor’s degree with 5&#43; years of pre-silicon RTL design experience. Demonstrated experience developing RTL for complex digital IP from specification through implementation handoff. Hands-on experience with ASIC low-power design methodologies, including UPF-based power intent and CDC/RDC analysis. Strong knowledge of ASIC design flows, including RTL design, logi