Senior Silicon Validation Methodology Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join a team at Micron where you will have the chance to own verification and end-to-end analysis of complex full-chip custom builds. Our advanced low-power and power management technologies span multiple categories, including high-speed memories. Collaborate closely with global development and verification team members, many of whom have decades of experience in memory engineering. This role will also offer cross-functional tasks that can broaden your abilities. Responsibilities Lead and define the approach for the verification activities within your areas of expertise in any project the team engages in. Provide verification support to build projects by simulating, analyzing, and debugging pre-silicon full-chip builds. Design test cases/stimuli aimed at broadening the functional coverage for HBM emerging memory architectures and features. Take part in the development of verification methodology and environments for advanced HBM and emerging memory products. Collaborate with international colleagues on building new verification flows to address challenges in HBM and emerging memory development. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Apply AI for automation of technical and non-technical processes. Minimum Qualifications More than 5 years of experience in pre-silicon verification. BE or MTech in Electronics Engineering or related field.

Who We Are Rubrik is one of the fastest-growing companies in Silicon Valley, revolutionizing data protection and management in the multi-cloud IT industry. Our mission is to unlock the power of data by organizing and protecting the world's business information, and we've built a forward-thinking, design-oriented brand that is changing how enterprises think about resilience. We don't wait for someone else to define the industry — we define it ourselves. Rubrik was the first platform to orchestrate data for hybrid and multi-cloud enterprises anytime, anywhere, blending future-proof architecture with consumer-grade simplicity. We're looking for people who produce extraordinary results, who are comfortable in ambiguity, and who are excited by hard problems. If you have a limitless drive and like to win, we want to talk to you. Who You Are As Rubrik's business increasingly runs on hyperscale cloud infrastructure, we're adding an individual contributor Senior Strategic Sourcing Manager to own the end-to-end, 360° relationship with our most strategic cloud and technology partners — including AWS, Google Cloud, and Microsoft — as well as other key strategic vendor relationships across the business. While strategic cloud and technology partnerships are the anchor of this position, you'll also flex into broader sourcing deals across the team's portfolio as priorities shift — negotiating agreements, running competitive sourcing events, and partnering cross-functionally wherever the business needs strong commercial leadership. You'll work closely with cross-functional partners including Engineering, IT, InfoSec, Legal, Finance, and Accounting. You're a self-starter who's comfortable operating with limited direction and full ownership of your domain — a pragmatic problem-solver who thrives in a fast-paced environment. You will report to the Head of Global Procurement and be accountable for savings, risk, and relationship health across your portfolio. What You'll Be Doing Strateg

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

We are now looking for a Senior Chip Design RTL Design Engineer for the Switch Silicon group. As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! What you'll be doing: Work in a combined design and verification team which develops some of the switch silicon core units. Plan and Design RTL units / blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance. Build reference models, verify and simulate chip blocks/entities according to specifications. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. What we need to see: B.Sc. in Electrical Engineering or Computer Engineering. 4&#43; years of experience in RTL design or RTL verification. Previous experience in networking - an advantage. A team player with good communication and interpersonal skills. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field. #LI-Hybrid <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Unique Opportunities Complete ownership of verification and end to end analysis of complex full chip custom designs with advanced low power and power management technologies spread across multiple categories such as memories that are capable of operating at high speeds. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on cross functional tasks that can widen your skill set. Responsibilities Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for HBM emerging memory architectures and features. Participate in developing verification methodology and verification environments for advanced HBM and emerging memory products. Co-work with international colleagues on developing new verification flows to take on the challenges in HBM and emerging memory design. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Applying AI for automation of technical and non - technical process is required. Minimum Qualifications: 5&#43; years of experience in pre-silicon verification BE or

... Address: Tata Teleservices Limited, 30/1, Silicon Terraces, B-Block, 2nd Floor, Hosur Main Road, Koramangala, Bangalore - 560095 Facility: TATA TELESERVICES - KA Qualification: Graduate Experience: 2 - 3 years Source: Sodexo India | Job Code: IJP567858

The Advanced Cell Technology Lead will be responsible for driving next-generation battery cell technology development, focusing on advanced lithium-ion chemistries, solid-state batteries, silicon-anode technology, high-energy-density cells, and emerging energy storage solutions. The role involves leading research, material evaluation, prototype development, technology roadmap creation, and commercialization of advanced cell technologies for EV and BESS applications. Source: Adani Group | Job ID: 60074

Job Details: Job Description: Do Something Wonderful At Intel, we put silicon at the center of the world’s most meaningful innovations. From personal computing and AI to cloud-scale data centers and edge platforms, our processors power technologies that touch billions of lives. If you’re passionate about building world-class silicon at massive scale, we want to build the future with you. The Team You’ll join Intel’s All Cores Engineering (ACE) organization, the team responsible for designing and delivering Intel’s industry‑leading CPU cores. Within ACE, the Atom group focuses on high‑efficiency, performance‑per‑watt optimized cores that enable everything from client platforms to emerging edge and scalable solutions. This is a hands‑on senior engineering role with direct impact on next‑generation CPU silicon. What You’ll Do As a Senior CPU Design Verification Engineer you will play a critical role in ensuring architectural correctness, functional robustness, and power‑efficient performance of Intel’s Atom CPU designs before first silicon. Key responsibilities include but not limited to the following: Lead pre‑silicon functional verification of complex CPU and SoC logic to ensure full compliance with architectural and microarchitectural specifications. Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments, ensuring comprehensive functional and coverage closure. Define, run, and analyze system‑level simulations to uncover functional, performance, power, and corner‑case issues. Debug and root‑cause complex RTL, microarchitecture, and integration issues; drive issues to resolution with design teams. Collaborate cross‑functionally with CPU architects, RTL de

Build the infrastructure that keeps every NVIDIA chip aligned from first spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs. When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss. We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment, at scale across the full portfolio. The strongest candidates in this role design the workflow before being asked to fix a program, and build the checks and automation that confirm alignment holds long after they've moved on to the next problem. What you’ll be doing: SMAC Workflow Methodology: Define manufacturing spec types, including schema and semantics, derived from system PORs and features. Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle. Production Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs ,ATE, SLT, BLT, L10&#43;, before silicon exposes the discrepancy. The goal is that misalignments surface in the workflow, not on the tester. E2E Program Integration & TPM Attestation: Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag. Alignment can't be assumed; it must be proven at every stage. Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready

Define the physical limits of what a chip can do, then break them! NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first principles thinking translates directly into product outcomes at scale. As GPU power density and thermal limits approach physical boundaries, the gap between system architecture needs and manufacturable, testable capabilities widens with every generation, and this role exists to close it. You wouldn't be maintaining existing solutions, you'd be identifying where physical constraints will erode NVIDIA's competitive edge before anyone else sees it coming, then building the cross-domain responses that ensure the next generation leapfrogs those limits entirely. The problems here don't have known answers yet: Every generation of NVIDIA silicon pushes closer to the limits of physics. The Co-Design Architect role isn't about optimizing within known bounds; it's about redrawing those bounds entirely. If you want your work to shape what's physically possible in the world's most demanding computing products, this is where that work happens. What you'll be doing: Power, Thermal & Packaging Limits Analysis: Gather and analyze the hard constraints of packaging, power delivery, and thermal dissipation against roadmap demands, predicting when those constraints will reduce competitiveness and acting before they do. Cross-Domain Solution Development: Develop solutions that span silicon features, packaging innovation, firmware and hardware co-design, and DFX updates, ensuring future products are not only performant but testable to the highest quality and reliability standards. Packaging Technology Evaluation: Assess emerging packaging technologies for their voltage/frequency, noise, reliability, and testability implications, determining which are worth adopting an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. The Senior Engineer – HBM Design for Test (DFT) is an experienced technical contributor responsible for the definition, implementation, integration, and support of DFT solutions across HBM core die and base die for current and next‑generation HBM products. This role focuses on driving defined DFT architectures , contributing to DFT specifications, and partnering with multi‑functional teams to ensure DFT features meet test, quality, and manufacturability requirements. The Senior Engineer works closely with DFT Architecture, Design Engineering, Product Engineering, Test, and DFT Verification to support successful tape‑out, silicon bring‑up, and qualification. Key Responsibilities Implement and integrate DFT features for assigned HBM core die and base die designs in alignment with established DFT architecture and guidelines Contribute to the development, review, and maintenance of DFT specifications, requirements, and implementation guidelines Ensure DFT implementations support high‑quality, efficient, and manufacturable HBM products Collaborate with Design Engineering, Product Engineering, Test, and DFT Verification to: T

About Graphcore At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary As a Senior Machine Learning Engineer in the Applied AI team at Graphcore, you will contribute to advancing AI technology by developing and optimising AI models tailored to our specialised hardware. You will work on large scale systems where performance is critical to the success of our projects. Working closely with the Software development and Research teams, you will play a critical role in identifying opportunities to innovate and differentiate Graphcore’s technology. We seek engineers with strong technical skills and an understanding of AI model implementation at scale, eager to make a tangible impact in this rapidly evolving field. The Team The Applied AI team’s role is to be proxies for our customers, we need to understand the latest AI models, applications, and software to ensure that Graphcore’s technology works seamlessly with the AI ecosystem and at scale. We build reference applications, contribute to key software libraries e.g. optimising kernels for efficiency on our hardware, and collaborate with the Research team to develop and publish novel ideas in domains such as efficient compute, model scaling and distributed training and inference of AI models for multiple modalities and applications. If you're excited about advancing the next gen

Senior HR Business Partner, Personal Systems Description - You want to change the world. So do we. HP started Silicon Valley over 80 years ago, and today, we’re the world’s most sustainable and just company in tech. At HP, you’ll find a global community that shares your values—and your ambition. We’ve been creating technology that shapes the future for more than 80 years, all while striving to make extraordinary contributions to humanity. Today, we're one of the most sustainable, just, and inclusive companies in tech—and stronger than ever. You’re looking for more than just a job; you’re looking to make a difference. That means creating something new. Something that matters. Something that changes the world for the better. The Senior HR Business Partner serves as a strategic advisor to senior leaders within HP's Personal Systems organization, one of the company's largest and most dynamic businesses. This role partners with senior leaders not only across a global business, but also will collaborate closely with Centers of Excellence and HR colleagues worldwide to deliver talent and organizational solutions that enable transformation and growth. The role will play a critical part in shaping global workforce strategy, organizational effectiveness, leadership capability, and culture to accelerate business outcomes. The successful candidate will influence key business decisions while helping leaders build high-performing organizations positioned for long-term growth. Key Responsibilities of the Sr. HRBP – Personal Systems role: Partner with business leaders to shape workforce and organizational strategies that enhance organizational effectiveness, strengthen leadership capability, accelerate talent outcomes, and foster a high-performance culture. Lead workforce planning, organizational design, change management, an

We are excited to welcome a creative and independent Production Security Software Engineer for the IC test and product engineering group in NVIDIA Networking Business Unit. NVIDIA Networking Business Unit has continuously reinvented itself over two decades. Our high-speed buses & network products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another and today we are known as the go-to place for “End-to-End High-Speed Ethernet and InfiniBand Solutions”. We're looking to grow our company and build our teams with smart people who can join us at the cutting-edge technology. We are seeking a security engineer who will thrive in our innovative environment, who will help make our Network Silicon ICs products (Switch, NIC, SmartNic) secure. You will collaborate with test engineers, test house, Design, IT, vendors and many other professionals in the organization for the development of tools and test infrastructure for enabling security features in test and in all of our processes. At NVIDIA, we foster a collaborative and inclusive culture where your ideas can make an immediate impact. If you are passionate about enabling of the highest quality Network products in the market, we want to hear from you! What you'll be doing: Lead all security aspects in the integrated circuit production engineering team, including Define with security architects how to introduce new features into the ICPE production line Work with test engineers to add security related features into the test program, work with HSM vendors to provision our production lines with required security appliances an work with the production lines team to ensure smooth integration into the lines. Own the regression system to ensure no security related issues in the line, Enforce security reviews in internal SW development and work with corporate tools to ensure securi

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. NVIDIA’s DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in the world—spanning 2.5D/3D AI data center platforms, Gaming and Enterprise GPUs, and complex SOCs powering Autonomous Machines, Robotics, and Industrial systems. You will innovate at scale, designing and prototyping breakthrough Test Architectures for reticle sized, multi-chiplet products—from RTL to verification to post-silicon ATE bring-up. Join a globally recognized team that consistently delivers breakthrough performance across multiple high-impact tape-outs each year. What you'll be doing: Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms. Collaborate with leading EDA vendors to shape tool capabilities that meet NVIDIA’s ambitious design goals, and partner with internal CAD teams to drive scalable, automated solutions. Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation. Own the full ATPG lifecycle—verification, coverage analysis, pattern generation, and ATE bring-up—across NVIDIA’s full product portfolio. Guide and mentor junior engineers, helping them navigate complex design