Signal Integrity Hardware Engineer Jobs

What You'll Do Midjourney is seeking physicists to develop revolutionary quantum hardware technologies. What We're Looking For Multiple years of experience working in experimental quantum physics (Ph.D.-level or similar) Proficiency in the design, implementation, and troubleshooting of experiments Hands-on experience with laser-based optical measurements Ability to work on-site (up to five days/week) in the San Francisco Bay Area Given the nature of the work, U.S. citizenship is required. Useful Experience: Broad familiarity with quantum computing and/or sensing platforms Track record of delivering cutting-edge systems that work outside the lab Strong physical intuition about fundamental signal origins and noise sources Hands-on experience with optics, optoelectronics, photodetectors, and optical fibers Familiarity with next-generation photonic technologies Experience inventing new tools and processes to address experimental challenges Proficiency using the latest AI tools to accelerate workflow Excellent data visualization and presentation skills

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Serve as the core technical individual contributor in design and validation of the on-chip controller and mixed signal circuitry in NAND Flash chips. Responsible for architecture development and product definition, system integration and full-chip and block-level validation planning and execution. Contribute to RTL design and implementation of the controller hardware, synthesis, APR and full timing closure as well as development of firmware code for NAND internal operations. Work closely with design teams both domestically and overseas on different projects. Employer will accept a Master’s degree in Electrical Engineering or related field. Position requires: 1. Verilog language; 2. Digital ASIC design methodology; 3. Mixed-mode design and validation; 4. Design or Verification CAD tools, including NCSim; 5. Design Compiler, Formality, or PrimeTime; 6. TCL, PERL, C, C++, or Python; and 7. Non-volatile memory design (NAND). The US base salary range that Micron Technology, Inc. estimates it could pay for this full-time position is $173,607.10 - $ 246,000.00 . For additional pay & benefits information, please refer to the requisition at Micron.com/careers. As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide

As a Staff Product Manager on Datadog's Self-Improving Products team, you will take a new product family from zero to one: a closed loop that watches how a customer's software and its users behave, ranks what is worth changing, proposes the change, proves whether it worked, and carries the result into the next cycle. Datadog already holds every piece this product needs, including behavioral data from Product Analytics and Session Replay, full-stack telemetry from APM, Log Management, Error Tracking, and Continuous Profiler, rollout control through Feature Flags and Experimentation, and a coding agent in Bits AI Dev Agent that opens verified pull requests from production signal. You will own assembling these into one product where the loop closes on its own. This is founding work with no precedent inside Datadog, and an opportunity to grow as a product leader by shaping the scope, recruiting the first design partners, and setting the quality bar for an AI-native product from the ground up. At Datadog, we place value in our office culture - the relationships that it builds, the creativity it brings to the table, and the collaboration of being together. We operate as a hybrid workplace to ensure our employees can create a work-life harmony that best fits them. What You'll Do: Set product direction for a new product family by defining the problems and desired outcomes, and partnering with engineering to find the narrowest first slice that proves the loop closes and delivers value to customers in phases. Own the product decisions at every stage of the loop: what signal is trustworthy enough to trigger an automated change, which opportunities rank highest and with what confidence, what a proposed change must contain before a customer merges it, what evidence proves it worked, and what the system remembers for the next cycle. Define the autonomy ladder and its limits, from suggestion, to draft, to auto-opened pull request, to auto-rollout, along with the cont

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In-depth understanding of analog / mixed signal circuits. Experience in Analog and Mixed signal Verification , understand the usage of tools like Virtuoso, primesim/ Finseim, Hspice, Xcellium, Simvision, Waveview. Experience in debugging complex Analog/Digital/Mixed-Signal circuits is mandatory. Hands on experience in writing Verilog Models. Verilog A/MS, RVM model writing. Hands on experience in building SPICE testbenches at Block, Fullchip Level. Hand on experience in building the COSIM/ Mixed signal verification environment. Hands on experience in SV, UVM based Verification Hands on experience in SV/PSL assertions. Good scripting skills using perl, python is a plus. Previous work experience in DRAM memory related fields and Must possess good communication, debugging skills and ability to work well in a team. Should be proactive in exploring and leveraging AI-related tools in day-to-day tasks. Proactively adopt approved AI tools to support verification workflows, scripting, and methodology improvements, maintaining full responsibility for technical decisions. Bachelor’s with 4-6 years of experience or Post Graduate Degree in Electronics Engineering or related engineering field required with 2-4 years of experience. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles & responsibilities can include but are not limited to: Define the global DL4 matrices (Turnaround time, overdue matrices, detection compliance, Statistical Bin Limits (SBL) reactions etc) Ensure all sites adhere to globally aligned DL4 workflows Drive global automation and AI enhancements (YIT, Auto-contain, auto-disposition, Smart Manufacturing & Artificial Intelligence (SMAI) assisted detection) Oversee universal alignment so DL4 signal signals behave the same across sites Monitor the Assembly and Test specifications Improvements and optimization in existing DL4 systems via automation systems Spec limits (Analog values and limits, SBL Bins, Product level ESD) Test coverage/DL4 improvements (based on lessons learnt, Material review boards and Fail Mode Registers(FMR)) Network standardization (Dispositions/problems) FMR, Failure analysis, Failure analysis modelling and Defense Line Correlations Test program review and release Collaborate with cross-functional teams from Product Engineering, Media Health, Global Quality, Advanced Packaging Technology Development and Test Systems Engineering and drive projects to further enhance defense line 4 capabilities Mandatory Requirements: Strong understanding of semiconductor device physics Experience in device modelling and simulation using TCAD (Silvaco, Sentaurus, etc), as well as compact modelling. P

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles & responsibilities can include but are not limited to: Define the global DL4 matrices (Turnaround time, overdue matrices, detection compliance, Statistical Bin Limits (SBL) reactions etc) Ensure all sites adhere to globally aligned DL4 workflows Drive global automation and AI enhancements (YIT, Auto-contain, auto-disposition, Smart Manufacturing & Artificial Intelligence (SMAI) assisted detection) Oversee universal alignment so DL4 signal signals behave the same across sites Monitor the Assembly and Test specifications Improvements and optimization in existing DL4 systems via automation systems Spec limits (Analog values and limits, SBL Bins, Product level ESD) Test coverage/DL4 improvements (based on lessons learnt, Material review boards and Fail Mode Registers(FMR)) Network standardization (Dispositions/problems) FMR, Failure analysis, Failure analysis modelling and Defense Line Correlations Test program review and release Collaborate with cross-functional teams from Product Engineering, Media Health, Global Quality, Advanced Packaging Technology Development and Test Systems Engineering and drive projects to further enhance defense line 4 capabilities Mandatory Requirements: Strong understanding of semiconductor device physics Experience or know-how in device modelling and simulation using TCAD (Silvaco, Sentaurus, etc), as well as compact modellin

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role Anthropic's RL Data Platform team builds the systems that produce, move, and serve the human data Claude learns from: the interfaces humans use to give feedback, the pipelines that turn raw feedback into training signal, and the tooling researchers use to launch, monitor, and inspect data collection. Every RL run depends on a steady supply of high-quality data - human feedback, expert demonstrations, graded transcripts - and when a researcher has an idea for new data on Monday, our job is to make it collectable by Wednesday and in the training mix by Friday. This is a full-stack, ownership-heavy role on a small, senior team. You'll design and ship web interfaces used by thousands of expert annotators, build the backend services and data pipelines behind them, and work directly with RL researchers to understand what data they need and why. You'll scope your own projects, make architectural calls, and see them through to production. We're looking for engineers who treat researchers as their users, build for reliability first, and care as much about the shape of the data leaving the system as the UI going into it. Key responsibilities Design, build, and operate the feedback and data collection interfaces used by human annotators, domain experts, and internal researchers. Build and maintain the backend services, APIs, and pipelines that route model samples to humans and return structured feedback to training. Own the reliability, latency, and usability of systems that run continuously against live model endpoints. Partner with RL researchers to translate loosely specified data needs into well-scoped collection campaigns and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level. Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation. Responsible for development of digital block layouts using auto placement and route tools Responsible for basic understanding of skill coding and automation Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. Guide team members in their execution of Sub block-level layouts & review their work Effectively communicating with Global engineering teams to assure the success of layout project. Responsible for the reducing the layout effort by using AI About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performa

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Micron’s Design Engineering team and help drive the future of memory innovation. This team develops groundbreaking digital, analog, and mixed-signal circuitry that powers advanced memory solutions. You will collaborate with global teams across design, verification, process, and product engineering to deliver high-quality, scalable technologies that transform how the world uses information. As a Memory Design Engineer specializing in HBM, you will contribute to the design, optimization, and validation of memory, logic, and analog circuits. You will partner closely with multi-functional engineering and manufacturing teams to support product development and ensure robust, efficient, and manufacturable solutions. Key Responsibilities Design, layout, and optimize memory, logic, and analog circuits for HBM products Perform parasitic modeling, validation, reticle experiments, and support tape-out revisions Complete layout processes including floor planning, placement, and routing Conduct circuit verification using industry-standard modeling and simulation tools Collaborate with multi-functional teams (design, verification, process, product engineering) to ensure manufacturability and product success Use AI supported design and simulation tools to enhance circuit modeling accuracy, improve design efficiency, and accelerate development cycles Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineerin

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Lead end-to-end layout execution of analog, mixed-signal, custom digital blocks and full-chip integration for HBM products. Own full-chip technical decisions covering analog, digital, memory, ESD, EM/IR and ensure optimal performance, power, and area (PPA). Technical Expertise : Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as: Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. Drive project planning and execution , including area/time estimation, scheduling, task delegation, and milestone tracking across multiple concurrent programs. Ensure timely delivery with quality , responsible for block-level and full-chip layouts meeting schedule commitments and quality expectations. Perform and oversee layout verification activities including LVS, DRC, Antenna checks, and ensure closure with proper documentation and audits. Lead and mentor the layout team , guiding junior engineers on sub-block execution, conducting design reviews, and enabling capability development. Drive innovation and productivity improvements , including adoption of AI/automation to reduce layout effort, improve turnaround time, and enhance quality. <li

Secure Every Identity, from AI to Human Identity is the key to unlocking the potential of AI. Okta secures AI by building the trusted, neutral infrastructure that enables organizations to safely embrace this new era. This work requires a relentless drive to solve complex challenges with real-world stakes. We are looking for builders and owners who operate with speed and urgency and execute with excellence. This is an opportunity to do career-defining work. We're all in on this mission. If you are too, let's talk. The Opportunity Okta is building an AI-enabled demand engine that uses signals, automation, and intelligent engagement to identify, qualify, route, and progress the right buyers more effectively. The AI Journey Operations Manager will own the business strategy, qualification framework, routing logic, operating model, and performance optimization for AI-assisted xDR capabilities across the Global Demand Center. This role is not primarily a platform administration or workflow-build role. It is a senior, cross-functional capability-owner role responsible for determining how AI-assisted qualification and engagement should operate, how it connects to human xDR and Sales follow-up, and how it contributes to measurable funnel and pipeline outcomes. The ideal candidate combines AI-enabled GTM experience, xDR/Sales process knowledge, demand generation, revenue operations, and journey strategy. They can translate business priorities into qualification logic, routing rules, AI engagement workflows, handoff requirements, measurement frameworks, and ongoing optimization plans. What You’ll Do Own AI xDR qualification strategy Define qualification frameworks for AI-assisted engagement across priority inbound, account-based, product-led, customer, and signal-triggered motions. Establish the fit, behavior, intent, engagement, and business-context criteria used to determine whether a lead or account should be engaged, progressed, routed, recycled, or suppressed. Partn

About Sentry Software runs the world and the pace is faster than ever. Sentry helps developers fix errors and performance issues before users notice, so teams can spend less time firefighting and more time building. Trusted by 200,000+ organizations, Sentry is today’s application monitoring standard and our team is building its AI-native future. About the role Issue Workflow is Sentry's primary product surface. Our issue platform processes billions events daily and turns them into actionable insights that help millions of developers fix bugs faster. As a Staff Software Engineer on the Issue Workflow team, you'll architect the systems that power this experience. You'll work at the intersection of high-scale distributed systems and product engineering, building real-time data pipelines, search backends, and analysis systems that surface signal from noise. This is product engineering at massive scale—where every architectural decision impacts millions of debugging sessions. You'll be the technical leader who shapes how Sentry groups issues, how we make search lightning-fast, how we enable sophisticated agentic workflows, and how we ensure that the product is performant even at billions-of-events scale. Your work will define what's possible for the most trafficked part of Sentry's platform. In this role you will Drive technical strategy and roadmap. Partner with engineering leadership, product, and design to shape the multi-quarter technical vision for Issue Workflow platform. Make strategic calls about architectural direction, technology choices, and technical debt. Ensure the team is building a strong foundation to scale with Sentry's growth. Solve complex performance and scalability challenges. Champion product quality and user experience. Build features that don't just work—they delight. You understand that milliseconds matter in the developer experience. You sweat the details of interfaces, error messages, loading states, and edge cases. You instrument everything s

About Sentry Software runs the world and the pace is faster than ever. Sentry helps developers fix errors and performance issues before users notice, so teams can spend less time firefighting and more time building. Trusted by 200,000+ organizations, Sentry is today’s application monitoring standard and our team is building its AI-native future. About the role Issue Workflow is Sentry's primary product surface. Our issue platform processes billions events daily and turns them into actionable insights that help millions of developers fix bugs faster. As a Staff Software Engineer on the Issue Workflow team, you'll architect the systems that power this experience. You'll work at the intersection of high-scale distributed systems and product engineering, building real-time data pipelines, search backends, and analysis systems that surface signal from noise. This is product engineering at massive scale—where every architectural decision impacts millions of debugging sessions. You'll be the technical leader who shapes how Sentry groups issues, how we make search lightning-fast, how we enable sophisticated agentic workflows, and how we ensure that the product is performant even at billions-of-events scale. Your work will define what's possible for the most trafficked part of Sentry's platform. In this role you will Drive technical strategy and roadmap. Partner with engineering leadership, product, and design to shape the multi-quarter technical vision for Issue Workflow platform. Make strategic calls about architectural direction, technology choices, and technical debt. Ensure the team is building a strong foundation to scale with Sentry's growth. Solve complex performance and scalability challenges. Champion product quality and user experience. Build features that don't just work—they delight. You understand that milliseconds matter in the developer experience. You sweat the details of interfaces, error messages, loading states, and edge cases. You instrument everything s

We believe that the way people interact with their finances will drastically improve in the next few years. We’re dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid’s network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. Our Fraud team's mission is to help companies detect and prevent fraud using Plaid's financial network data. We believe that transaction patterns, device signals, identity linkages, and behavioral data are dramatically underleveraged tools in fraud prevention. Our products — including Protect and Signal — operate at network scale and depend on real-world investigation and research to stay ahead of adaptive adversaries. As a Senior Fraud Researcher, you will sit at the intersection of live fraud investigation, applied data science, and product innovation. You will lead complex investigations, translate findings into detection improvements, and collaborate tightly with Data Science, ML, and Product teams to shape the next generation of Plaid's fraud capabilities. This is not a purely operational role — your research directly drives features, model inputs, and product design. Responsibilities: Live Fraud Investigation & Reconstruction Lead investigations into complex fraud cases across identities, accounts, devices, and transaction surfaces Provide support to day-to-day fraud operations including SEVs and alert triage Reconstruct attacker sequences and hypothesize actor intent and tooling Distill p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skills in planning, area/time estimation, scheduling, and execution to meet project scheduling multiple project environment. Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Qualification/Requirements 8 to 15 years' experience in analog/custom layout build in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc. Ability to understand build constraints and implement high-