Soc Architecture And Design Engineer Jobs

Graphcore is a globally recognized leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and datacentre hardware that provide the specialized processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, we are working to enable Artificial Super Intelligence and ensure that its benefits are accessible to everyone. We are developing the next generation of AI compute, a large-scale system-on-chip (SoC) designed to power future high-performance AI systems. As the Director of Post Silicon Validation, you will be responsible for leading the Bristol team, enabling pre-production software to run reliably on new silicon quickly and efficiently, before showing that the silicon meets the highest standards of quality, reliability and functionality, ready for production deployment. Reporting to the Senior Director of Post Silicon Validation, you will manage, develop and grow the Post Silicon Validation team in Bristol, delivering post-silicon validation across the full AI SoC, working across silicon, firmware, and platform levels. The role requires a deep technical understanding, strong hands-on debug experience, and the ability to collaborate effectively with hardware, software, and systems engineering teams. Responsibilities Manage, develop and grow the Post Silicon Validation team in Bristol: The Post Silicon Validation team is relatively new, with a strong remit and growing quickly to help Graphcore bring up new silicon quickly and effectively. Play a significant role in the definition, planning and execution of chip bringup activities: Develop and refine the overall post-silicon validation approach for our AI SoCs, ensuring reliable and timely delivery of validated silicon, architectural correctness, feature r

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Member of Technical Staff, SoC Power and Physical Architect in the Next-generation HBM Architecture Team, you will drive SoC-level specification 3D-stacked, high-performance memories. Apply your knowledge to analyze SoC trade-offs in close collaboration with peer architecture and design teams. Drive power architecture, physical planning, and early SoC design activities, including definition of IP interfaces (e.g., signals, power delivery), clocking, power sequencing, design-for-test, floorplanning, and specification development. Responsibilities: Define clocking architectures, power sequencing, power delivery, and on-die signal interfaces. Define and analyze on-die power delivery networks (PDN) and full-chip thermal implications, including power hot-spot identification and mitigation. Define DFT architectures (e.g., scan chain topology) and set verification requirements. Define SoC floorplans in collaboration with physical designers. Compose and maintain clear SoC physical documentation. Preferred Qualifications: Experie

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an experienced and motivated System IP RTL Design Lead to drive the definition and implementation of complex datacenter class IP for our next-generation semiconductor products. The ideal candidate possesses a deep understanding of System IP and SoC architecture, IP integration challenges, and is adept at leading a design team to deliver high-quality, scalable IP solutions. This role requires strong hands-on technical leadership, excellent communication skills, and a proven track record in the successful delivery of silicon IP. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned IP / SoC design leader with 20+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration. Skilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs. Experienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations. A proactive problem so

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The Architecture team at Tenstorrent is designing the central compute chiplet that powers our next generation automotive SoC. This role is about turning real world automotive and safety requirements into architecture that performs, scales, and ships fast and reliably. If you think silicon design should start with clarity and end with confidence, this is where your experience makes the biggest impact. This role is remote, based in Munich, Germany. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Approach design with a systems mindset, always thinking in trade offs, not just specs and block diagrams. Bring deep knowledge of SoC architecture, from interconnects and I/O to memory and CPUs. Confident working within performance, power, and reliability constraints. Familiar with, or eager to dive into, functional safety, ISO 26262, and automotive grade design challenges. What We Need Someone to architect and specify one or more chiplets in the robotics and automotive family. 5+ years of experience translating high level requirements into detailed architectural direction. Ability to identify impactful features that boost PPA, safety, and reliab

Datadog’s Implementation Services team helps customers implement and deploy Datadog quickly. Our team of architects leads the discovery, design, build, and launch of the Datadog platform to help customers accelerate time to value and get the most out of their investment. As a member of our team, you will be responsible for developing the technical roadmap for a customer’s implementation, and leading them through it every step of the way. At Datadog, we place value in our office culture - the relationships and collaboration it builds and the creativity it brings to the table. We operate as a hybrid workplace to ensure our Datadogs can create a work-life harmony that best fits them. What You’ll Do: Design and guide execution of Datadog implementations, including gathering requirements, building technical architecture, and supporting deployment and launch Guide customer onboarding through co-development working sessions and assist when they run into roadblocks Write automation and design architecture for deployment templates Manage the operation of implementation projects Collaborate with other teams, including Customer Success, Technical Account Management, and Sales to deliver an exceptional onboarding experience Who You Are: Experience designing and delivering technical solutions for DevOps Monitoring or architecture systems Hands-on experience with cloud platforms (AWS, Azure, GCP) and compute technologies (EC2, serverless, VMware, VMs, Docker, Kubernetes). Experience with Config Management, IAC and CI/CD tools, including Ansible, Puppet, Terraform, Chef, Jenkins, Circle CI, GitHub Actions, Azure Pipelines, etc… Experience programming/scripting with any of the following: Java, Python, Ruby, Go, Node.JS, PHP, and .NET etc Background in security operations, including SOC management, SIEM tooling (e.g. Splunk Professional Services), and designing or supporting zero-trust networking architectures Successful track record with 5+ years exper

Datadog’s Implementation Services team helps customers implement and deploy Datadog quickly. Our team of architects leads the discovery, design, build, and launch of the Datadog platform to help customers accelerate time to value and get the most out of their investment. As a member of our team, you will be responsible for developing the technical roadmap for a customer’s implementation, and leading them through it every step of the way. At Datadog, we place value in our office culture - the relationships and collaboration it builds and the creativity it brings to the table. We operate as a hybrid workplace to ensure our Datadogs can create a work-life harmony that best fits them. What You’ll Do: Design and guide execution of Datadog implementations, including gathering requirements, building technical architecture, and supporting deployment and launch Guide customer onboarding through co-development working sessions and assist when they run into roadblocks Write automation and design architecture for deployment templates Manage the operation of implementation projects Collaborate with other teams, including Customer Success, Technical Account Management, and Sales to deliver an exceptional onboarding experience Who You Are: Experience designing and delivering technical solutions for DevOps Monitoring or architecture systems Hands-on experience with cloud platforms (AWS, Azure, GCP) and compute technologies (EC2, serverless, VMware, VMs, Docker, Kubernetes). Experience with Config Management, IAC and CI/CD tools, including Ansible, Puppet, Terraform, Chef, Jenkins, Circle CI, GitHub Actions, Azure Pipelines, etc… Experience programming/scripting with any of the following: Java, Python, Ruby, Go, Node.JS, PHP, and .NET etc Background in security operations, including SOC management, SIEM tooling (e.g. Splunk Professional Services), and designing or supporting zero-trust networking architectures Successful track record with 6+ years exper

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we’re building cutting-edge hardware and software solutions that power AI, HPC, and general-purpose workloads. As a Performance Architect on our Platform Architecture team, you’ll work across ML software stacks, compilers, CPU design, cache coherency protocols, and interconnect fabrics to shape the future of high-performance systems. This role is all about bridging software execution and silicon design—making data-driven decisions that directly influence our SoC performance. This role is remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Passionate about solving complex system-level performance problems. Comfortable working across hardware and software boundaries. Analytical and data-driven, with a talent for turning workloads into architectural insights. Collaborative, thriving in cross-functional teams spanning compilers, CPU, and interconnect. Excited to shape the future of AI/HPC platforms through performance architecture. What We Need BS/MS/PhD in EE, ECE, CE, or CS Deep understanding of NoC topologies, routing algorithms, QoS, and traffic scheduling. Expertise in cache coherenc

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. The Role We are seeking a thorough SOC Physical Verification & Integration Specialist to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks. You will act as the critical bridge between block-level implementation, top-level integration, and final foundry signoff, ensuring that complex physical bottlenecks are resolved without compromising power, performance, or area (PPA). Key Responsibilities Top-Level Physical Integration: Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs). Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration. Hierarchical Verification Methodology: Architect and deploy highly efficient, hierarchical physical verification (PV) flows. Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs. Signoff Execution & Debugging: Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry-standard tools (e.g., Siemens Calibre) at advanced process nodes (5nm, 3nm, or below). Cross-Functional Collaboration: Partner tightly with the Physical Design (PD

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat: Find critical silicon issues earlier — often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role. Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies. What you’ll be doing: Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs. Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready. Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation. Deve

Datadog’s Implementation Services team helps customers implement and deploy Datadog quickly and successfully. Our team of architects leads the discovery, design, build, and launch of the Datadog platform to help customers accelerate time to value and get the most out of their investment. As a Senior Services Architect focused on Security and Cloud SIEM, you will help customers design, implement, and operationalize Datadog’s security capabilities across cloud, infrastructure, application, and log data sources. You will lead structured, outcome-driven professional services engagements delivered through a day-based professional services delivery model, partnering directly with customers through co-development working sessions, architecture workshops, implementation planning, and operational handoff. This role is ideal for someone who combines customer-facing consulting experience with strong cybersecurity knowledge, hands-on Cloud SIEM implementation skills, and an understanding of security control frameworks such as NIST 800-53, the NIST Cybersecurity Framework, CIS Controls, MITRE ATT&CK, SOC 2, PCI, HIPAA, ISO 27001, or similar standards. At Datadog, we place value in our office culture — the relationships and collaboration it builds and the creativity it brings to the table. We operate as a hybrid workplace to ensure our Datadogs can create a work-life harmony that best fits them. What You’ll Do: Design and guide execution of Datadog implementations, focusing on Security and Cloud SIEM deployment, including discovery, requirements gathering, technical architecture, deployment planning, and launch. Partner with customers to map security requirements, controls, and monitoring objectives to Datadog capabilities, including frameworks such as NIST 800-53, NIST Cybersecurity Framework, CIS Controls, MITRE ATT&CK, SOC 2, PCI, HIPAA, ISO 27001, or similar standards. Advise customers on security data strategy, including log source prioritization, parsing, normalizat

GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and compliance risk, and accelerate digital transformation. More than 50 million registered users and more than 50% of the Fortune 100* trust GitLab to ship better, more secure software faster. The same principles built into our products are reflected in how our team works: we embrace AI as a core productivity multiplier, with all team members expected to incorporate AI into their daily workflows to drive efficiency, innovation, and impact. GitLab is where careers accelerate, innovation flourishes, and every voice is valued. Our high-performance culture is driven by our values and continuous knowledge exchange, enabling our team members to reach their full potential while collaborating with industry leaders to solve complex problems. Co-create the future with us as we build technology that transforms how the world develops software. * Fortune 500® is a registered trademark of Fortune Media IP Limited, used under license. Claim based on GitLab data. Fortune 100 refers to the top 20% ranked companies in the 2025 Fortune 500 list, published in June 2025. Fortune and Fortune Media IP Limited are not affiliated with, and do not endorse products or services of GitLab. An overview of this role As a Senior Professional Services Technical Architect, Security at GitLab, you'll lead the design and implementation of secure enterprise solutions for Professional Services clients across AMER. You'll assess complex security architectures, guide security tool and CI/CD migrations, including legacy tools such as Jenkins, and implement GitLab security capabilities to help customers meet compliance frameworks such as NIST 800-53, ISO 27001, and SOC 2. This role requires depth in secure reference architecture design across cloud security, identity management, vulnerability management, and deployment choices

Most security assurance work is reactive: a customer asks, a team scrambles, an answer goes out. This role exists to end that cycle. As a Senior Staff Analyst, you’ll own a named portfolio of our most significant customers from a security perspective, and get ahead of what they need — their regulatory environment, their audit calendar, their risk appetite, their control expectations — well enough to have the evidence ready before the request arrives. You’ll lead customer security audits hands-on, sit across from customer security teams as a peer rather than a form-filler, and build account security plans that make the next assessment predictable instead of painful. This is deliberately a hands-on senior individual contributor role. You’ll spend your time in audits, in customer conversations, and in the detail of controls and evidence — not in a management chain. If you’ve got deep SOC 2 and ISO 27001 knowledge, real technical range across cloud architecture, identity and vulnerability management, and the presence to hold a room with a sceptical CISO, this is a portfolio you can genuinely own. Here’s a breakdown of what you’ll do (not all of it, just the important stuff): Own a portfolio of strategic accounts as their dedicated security point of contact, building durable relationships with their security, risk, compliance and procurement teams. Lead customer security audits and assessments hands-on — scoping, preparing evidence, running the sessions, defending control design and driving findings to closure with internal owners. Build and maintain an account security plan for each account: their frameworks and regulators, audit and reassessment cycles, known concerns, open items and the roadmap commitments they care about. Anticipate requirements before they’re raised, tracking regulatory change, industry expectations and each account’s compliance calendar so documentation and evidence are staged in advance. Act

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The DRAM Architecture team is responsible for defining the system‑level and silicon‑level architectures that enable Micron’s memory products. The team works across technology generations and product lines, collaborating with design, product, systems, and ecosystem partners to deliver scalable, reliable, and high‑performance memory solutions aligned with customer and market needs. This role provides senior‑level architectural leadership to help shape Micron’s next‑generation DRAM products. As a Distinguished Member of Technical Staff, you will influence memory architecture decisions across semiconductor chips, assembly methods, component units, and system interfaces, contributing to both near‑term product execution and long‑term technology direction. This role requires AI proficiency or AI‑enabled ways of working. Responsibilities: • Define and evolve DRAM system architectures that address performance, capacity scaling, reliability (RAS), and observability requirements. • Collaborate across functions to evaluate architectural trade‑offs spanning DRAM silicon, packaging, modules, boards, and system platforms. • Influence host memory controller and platform architecture through technical engagement with CPU, GPU, and SoC partners. • Contribute to RAS and telemetry feature definition, translating system‑level needs into implementable architectural concepts. • Support exploration of emerging memory technologies and assess their impact on future product roadmaps. • Engage with cus

About Graphcore At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI’s rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference. Reporting to the Director of Silicon Architecture, the SoC Architects are responsible for the design, specification, modelling and integration of sub-systems within complex, high performance and highly integrated silicon devices at the forefront of AI acceleration technology. The role involves close collaboration with other groups, including architecture, silicon design, verification, hardware and software teams. The Team The Silicon Architecture Team sits within the COO group. The SoC architects are responsible for the architectural specification, integration, modelling, validation and evaluation of numerous critical&nb