Advanced Cmos Device And Process Integration Engineer Jobs

Zoox’s Advanced Hardware Engineering team is in charge of delivering all the autonomous hardware, infotainment electronic control units and electrical components that go into Zoox’s future fleet of self-driving vehicles. At the heart of our hardware architecture is the Primary Compute Unit (PCU) - the compute system that runs the AI stack that enables the vehicle to drive autonomously. We are looking for a seasoned technical program manager own the PCU program end-to-end, including the integrated program schedule. In this role, you will work cross-functionally with our vehicle engineering, systems engineering, software, safety, supply chain, quality, manufacturing and integration teams to achieve our strategic objectives and tactical milestones. You will develop project schedules with numerous dependencies, map program milestones to company milestones, flag and mitigate risks, estimate and maintain budgets, identify solutions to complex problems, navigate ambiguity, all the while holding teams accountable and clearly communicating expectations and ongoing progress. As with any startup, we move fast here at Zoox, and many candidates will be asked from time to time to wear many hats. We would love to hear from you if you are up for solving very challenging problems across numerous cross-functional teams, delivering milestones with numerous dependencies, and scaling your impact by developing and adopting structured ways of working. Additionally, if you are an expert at herding cats and influencing without formal authority, then this role was made for you! In this role, you will: Drive the PCU program forward with thought and energetic leadership, including supporting architecture alignment, hardware development, validation, integration, cross-functional alignment and company-wide communication. This will be done in close partnership with the technical lead and other core team members across multiple departments. Work with department le

We are seeking a highly skilled and visionary Staff Signal and Power Integrity (SI/PI) Engineer to join our advanced hardware engineering team. In this role, you will be the definitive technical expert responsible for ensuring the signal quality, timing, and power delivery robustness of our most complex, next-generation robotaxi electronic systems. As a technical pillar within the organization, you will define overarching SI/PI architectures, establish company-wide simulation methodologies, guide electrical design and layout teams, and own the end-to-end sign-off for cutting-edge high-speed interfaces. In This Role, You Will Lead the SI/PI architecture and define constraints for next-generation, high-complexity, high-density printed circuit boards (PCBs) and overall system design. Collaborate at an architectural level with hardware design, silicon vendors, PCB layout, and mechanical engineering teams to define layer stack-ups, routing strategies, component placement, and power delivery architectures. Analyze, optimize, and sign off on advanced high-speed serial links (PCIe, Ethernet, MIPI, GMSL) and memory interfaces (LPDDR). Provide expert-level design guidance and validation for automotive-specific communication and audio protocols (A2B). Architect and conduct comprehensive Power Delivery Network (PDN) analysis, including DC IR drop, AC impedance modeling, and transient response analysis to ensure stable power delivery across complex multi-board systems. Drive the development of advanced SI/PI routing rules, simulation methodologies, automation scripts, and sign-off processes for the hardware engineering department. Tackle the most complex, unprecedented signal and power integrity challenges, performing hands-on root-cause analysis, lab measurements, and correlating simulation models with real-world testing. Act as a technical mentor and subject matter expert, elevating the SI/PI capabiliti

As Manager, Sensor Integration/Cleaning HW, you will lead a team responsible for ensuring Zoox vehicles can operate safely and reliably in real-world environments. You will manage a multidisciplinary team of engineers designing, integrating, validating, and launching sensor assemblies and sensor cleaning systems that maintain the performance of our autonomy sensors across a wide range of environmental conditions. You will drive your team's engineering solutions and program execution to ensure sensors remain within operational specifications, minimize contamination-related failures, optimize for supply chain and volume manufacturing, improve vehicle availability and serviceability, and support the scalable deployment of Zoox autonomous vehicles. In This Role, You Will Lead, mentor, and grow a team of mechanical, electrical, and systems engineers developing sensor assemblies and sensor cleaning systems for Zoox's autonomous vehicle fleet. Own program delivery for sensor integration and sensor cleaning hardware, from concept through validation, launch, and fleet support. Set technical direction and review key design decisions across mechanical packaging, electrical integration, and system-level architecture for sensor and cleaning subsystems. Partner with sensor performance, perception, test, manufacturing, and quality teams to ensure designs meet performance, reliability, and manufacturability requirements. Manage program scope, schedule, and resourcing across multiple concurrent sensor integration and cleaning projects. Drive cross-functional design reviews, DFMEA/PFMEA processes, and validation planning to de-risk programs ahead of production. Represent the team in front of engineering leadership, communicating program status, technical tradeoffs, and risks. Recruit, develop, and retain engineering talent, and build a strong culture of technical rigor and ownership within the team. </di

What We're Looking For: We're looking for photonics packaging engineers to contribute to, and own aspects of the A-0 and A-1 packages. This role bridges the classically divided photonics and advanced packaging skillsets, and thus is an unique point in our team. Ideal Background: Experience with integrated photonics package assemblies with multiple dies Experience with integrated circuit MCM assemblies with multiple heterogeneous materials, including compound semiconductors Understanding of photonics concepts, such as mode field diameters, mode mismatch, polarization, etc. Nice to Have: Experience with large device count photonic assemblies Experience with clear underfill Experience with high density fiber attach Experience with large substrate size photonic MCM assemblies Hands-on experience with PIC design

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize flip chip attach processes including bump formation, placement, reflow, and underfill for high-performance semiconductor packages. Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps) and substrate pad finishes for robust interconnect performance. Drive package integration from die to substrate, ensuring alignment, coplanarity, and yield optimization. Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding, head-in-pillow, and interconnect defects. Collaborate with substrate vendors, OSATs, and internal teams to define design rules (pad pitch, bump pitch, keep-outs, stack-ups). Lead process development for reflow profiles, flux selection, cleaning, and underfill dispense/cure. Perform root cause analysis of assembly and reliability failures using cross- sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manufacturing teams to ensure robust package performance from concept through high-volume production. Required Technical Skills: Strong experience in flip chip packaging and assembly processes for semiconductor devices. Deep understanding of bumping technologies (solder bumps, Cu pillar, micro- bumps) and UBM/metallization systems. Experience with underfill materials, dispense techniques, flow behavior, and cure processes. Understanding of thermo-mechanical behavior in flip chip assemblies (CTE mismatch, warpage, solder

We’re looking for a hands-on process and materials engineer to own wafer level molding and underfill processes, material qualification, and assembly integration across development and manufacturing. Summary: Seeking an experienced engineer to lead wafer level mold and underfill process development for advanced semiconductor packages (fan-out wafer level packaging, 2.5D/3D, chiplet). This role spans mold compound and underfill material selection and qualification, wafer level molding and encapsulation processes, underfill dispense and cure, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize wafer level molding processes including compression molding, transfer molding, and mold underfill (MUF) for fan-out and advanced heterogeneous packages. Own mold compound and underfill material selection and qualification, including evaluation of filler content, CTE, modulus, Tg, viscosity, and moisture uptake to meet thermo-mechanical and reliability requirements. Drive underfill process development including capillary underfill (CUF) dispense strategies, flow and void optimization, and cure profile development for high-density flip chip and chiplet assemblies. Evaluate and mitigate assembly risks including warpage, delamination, void formation, bleed-out, mold flash, and filler settling; define process windows and controls to ensure repeatable yield across wafer and panel formats. Collaborate with OSATs and material suppliers to qualify mold and underfill materials, define dispense and cure equipment requirements, and manage process transfers into production. Lead characterization of mold and underfill material properties (viscosity, gel time, cure kinetics, adhesion, CTE, modulus) and correlate material behavior to process outcomes and package reliability. Work closely with thermal mechanical modeling teams to model solder joint reliability of bump interconnects with va

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out). This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities Own end-to-end bump interconnect development for both ubump (micro-bump) and C4 processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip attach for high-performance semiconductor packages. Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys) interconnects, including UBM selection and pad finish specifications for both chip-side and interposer capture pads. Develop and own design rules for bump interconnects including pitch, bump diameter, standoff height, keep-outs, and land pad geometry for both the chip side and interposer or substrate capture pads. Lead RDL (redistribution layer) process development including electroplating of Cu RDL traces, via fills, and pad finishes; define RDL design rules for line/space, via diameter, and layer stack-up to meet electrical and reliability requirements. Collaborate with OSATs and bumping foundries to qualify ubump and C4 bumping processes, drive design rule alignment, and manage process transfers into production. Evaluate and mitigate bump interconnect assembly risks including non-wet opens, voiding, head- in-pillow, intermetallic growth, and joint fatigue failures across both ubump and C4 interconnect types. Perform root cause analysis of assembly and reliability failures using cross-sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manu

About the role : Join K Health as we partner with the nation's top-rated hospital systems to close care gaps by launching completely Virtual Comprehensive Care Clinics. We are seeking a full-time, board-certified Family Nurse Practitioners who will deliver fully remote text and video-based acute care, encompassing preventive care, sick visits, and chronic condition management. The ideal candidate must be licensed in FL, NJ, NY, MA, VA and/or hold active NLC. You will be responsible for maintaining a strong rapport with your patients, representing K Health and our clinical partners, while providing world-class remote care. You are comfortable practicing the full spectrum of comprehensive care, including pediatrics and mental health. Work from the comfort of your home and deliver care to those who need it the most, backed by K Health's cutting-edge clinical-grade AI Platform. Our virtual clinics are fully supported 24/7 by a dedicated team of Care Concierge, Clinical Operations, and technical support staff, which greatly reduces your administrative burden. What you'll be doing: Provide video-based, comprehensive clinical care that encompasses Acute Care, including pediatrics and mental health Work regular weekend day shifts (7a-7p Sat & Sun +1 Weekday) Support physicians with Epic inbox management (labs, imaging, patient questions, etc.) Educate patients on appropriate treatments and care plans for their health needs Prescribe medication and refills as appropriate Drive high-quality care with a focus on patient outcomes Elevate remote care; provide compassionate and meaningful care Think on your feet to devise creative solutions to problems that arise or escalate as appropriate Collaborate with Care Team Members Perform against challenging goals with a best-in-class team What we're looking for: 2+ years of clinical practice experience as a Family Nurse Practitioner in a Primary Care setting Licensed in FL, NJ, NY, MA and/or hold active NLC Must have mi

About the role : Join K Health as we partner with the nation's top-rated hospital systems to close care gaps by launching completely Virtual Comprehensive Care Clinics. We are seeking a full-time, board-certified Family Nurse Practitioners who will deliver fully remote text and video-based acute care, encompassing preventive care, sick visits, and chronic condition management. The ideal candidate must be licensed in FL, NJ, NY, MA, VA and/or hold active NLC. You will be responsible for maintaining a strong rapport with your patients, representing K Health and our clinical partners, while providing world-class remote care. You are comfortable practicing the full spectrum of comprehensive care, including pediatrics and mental health. Work from the comfort of your home and deliver care to those who need it the most, backed by K Health's cutting-edge clinical-grade AI Platform. Our virtual clinics are fully supported 24/7 by a dedicated team of Care Concierge, Clinical Operations, and technical support staff, which greatly reduces your administrative burden. What you'll be doing: Provide video-based, comprehensive clinical care that encompasses Acute Care, including pediatrics and mental health Must be able to work Monday and Friday with flexibility over starting hours (i.e., 7 am-12:30 pm ET) Support physicians with Epic inbox management (labs, imaging, patient questions, etc.) Educate patients on appropriate treatments and care plans for their health needs Prescribe medication and refills as appropriate Drive high-quality care with a focus on patient outcomes Elevate remote care; provide compassionate and meaningful care Think on your feet to devise creative solutions to problems that arise or escalate as appropriate Collaborate with Care Team Members Perform against challenging goals with a best-in-class team What we're looking for: 2+ years of clinical practice experience as a Family Nurse Practitioner in a Primary Care setting Licensed in FL, NJ, NY, MA

Graphcore is a globally recognized leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialized processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. RESPONSIBILITIES Responsible for the maintaining all the network fabrics and network topologies operating at peak performance on Graphcore Data centers housing AI server platforms. Collaborate closely with our Network architecture team through all phases of the design and development lifecycle — from concept to deployment — ensuring timely, high-quality, and stable high-speed network fabrics. Primary support of deployed internal fabrics in our AI Datacenters. Direct escalation for Hardware, Link and, Performance issues on network fabrics. Escalation support for customer network fabrics (aligned to reference arch.) Triage day-to-day network topologies (scale-up, scale-out, and front-end networks) issues of Fabrics deployed in Graphcore Datacenters. REQUIREMENTS Bachelor’s, master’s degree or equivalent experience in Network Engineering/Security, Information Technology, Computer Science, Computer engineering, or a related field. 9+ years of hands-on experience in network engineering and 3+ years supporting networking on AI or Hyperscale Datacenters. Knowledge of Remote Direct Memory Access (RDMA) and its implementations, specifically ROCEv2 or InfiniBand Knowledge of Lossless network – Experience with congestion control and lossless Ethernet technologies including PDF, ECN and DCQCN. Versed in High-Bandwidth networ

We are seeking a highly versatile Sensor & Hardware Safety Engineer to bridge the gap between rigorous hardware reliability and real-world system behavior. In this hybrid role, you will be responsible for 50% hardware-level Functional Safety (ISO 26262) and 50% system-level sensor safety (SOTIF / ISO 21448). You will ensure that our custom hardware meets strict ASIL compliance while guaranteeing our advanced sensor suites (Cameras, LiDAR, Radar) operate safely through perception edge-cases and environmental challenges. In This Role, You Will: Evaluate supplier technical documentation for advanced imagers, microprocessors, and SoCs to verify SEooC and AoU alignment. Assess vendor deliverables to guarantee ASIL standards are met for firmware/software maturity and diagnostic systems. Execute board-level FMEDA for sophisticated integrated circuits, including FPGAs and microcontrollers. Partner with Software, FW, and EE departments to define architectural requirements that enhance diagnostic monitoring. Support the V&V team in developing SOTIF-compliant simulation and physical test protocols for edge-case scenarios. Qualifications Minimum of a B.S. in Automotive, Robotics, Aerospace, or Electrical Engineering. At least 3 years of professional experience involving board bring-up, silicon validation, or hardware design. Understanding of SOTIF and ISO 26262 safety protocols. Strong interpersonal and professional communication capabilities within a collaborative environment Bonus Qualifications ISO 26262 professional certification (CFSP or CFSE). Background in automotive-grade hardware validation and design. Experience utilizing traceability platforms like JAMA or Polarion. Familiarity with industry standards including IEC 61508, DO-254, and DO-178C during board bring-up.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II. Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability. Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementati

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure. A hands-on problem solver who excels at debugging and driving signoff through complex verification flows. A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces. A mentor and technical leader passionate about building efficient, manufacturable silicon. What We Need BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verif

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes. Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs. Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows. Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independent