Band6 Jobs

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description As a key leader within High Bandwidth Memory (HBM) Product Engineering Media Health team, you will spearhead and develop a high performing team driving both intrinsic and extrinsic reliability test development and execution for Micron’s latest HBM products, both on DRAM and Interface die and a stacked product. Your responsibility is to drive extrinsic DPM reduction (Time 0 and Field DPM) and lead the intrinsic reliability charter, along with optimized Manufacturing Test Flow to meet critical KPI’s Quality, Cost and Cycle Time. You will be leading the team to characterize the products from reliability aspect, identify the reliability gaps, working on root cause and resolution of qual and RMA failures pertaining to defectivity and intrinsic reliability margin and drive fab process improvement driven by the qual failures. Additionally, your team will also be the key person in frontend process conversion, where you will work with Fab, TD, GQ teams to establish robust business process for process conversions to facilitate yield improvements, DPM and Cost Reduction. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. Responsibilities will include, but are not limited to: Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures. Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is

NVIDIA Networking is a leading provider of innovative end-to-end InfiniBand and Ethernet connectivity solutions for servers and storage. Our portfolio includes adapter cards, switches, cables, and software designed to optimize Data Center performance with industry-leading bandwidth and scalability. We serve diverse sectors such as high-performance computing, enterprise, cloud computing, and Web 2.0. Our mission is to stay ahead of the market by delivering groundbreaking products and services. Our Ethernet solutions are tailored for industries like Media & Entertainment and any domain that benefits from advanced DataStream and TCP/IP acceleration. What You’ll Be Doing: Lead a team of 8+ mechanical design engineers. Define priorities, create project plans, and allocate resources for mechanical programs in coordination with Product Managers. Drive all electro-mechanical, automated JIG and thermal design aspects, of production test setups, ensure readiness of test and assembly infrastructure for high-volume manufacturing. Develop multiple early design concepts in fast-paced product development cycles. Lead task forces to investigate and resolve production issues, reliability concerns, and conduct failure analysis. Perform risk assessments and implement mitigation strategies during product design. What We Need to See: B.Sc. in Mechanical Engineering or higher. 10+ overall years of relevant experience including 4+ years of experience managing teams of engineers in R&D environment. Proven expertise in developing, testing, and manufacturing of complex automated connection systems with precise moving parts, pneumatic and electro-mechanical systems design. Strong hands-on experience with 3D CAD tools (Creo preferred) static and dynamic mechanical simulation Solid background in designing components and sub systems an

We are looking for an innovative thermal solutions integration Engineer. NVIDIA offers you to be a part of the System Product Engineering group and be responsible for assuring the best quality products to be a sale and deliver to NVIDIA’ s customers. The job provides deep knowledge of NVIDIA systems, a system-level view of our solutions, and a dynamic and positive working environment and offers the candidates the opportunity to take a major role in our testing strategy by leading our thermal solutions integration and testing for the company production. NVIDIA Networking unit has continuously reinvented itself over two decades. Our high-speed buses & network products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting “End-to-End High-Speed Ethernet and InfiniBand Solutions” We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. If you are passionate about enabling the highest quality Network products that will change the world, we want to hear from you! What You’ll Be Doing: Integration and testing of next-generation, large-scale thermal, pressure, and liquid management solutions. Perform qualification tests for cutting edge cooling and sensing solution. Analyse and summarize thermal performance data and fluid dynamics results to support design reviews and decision-making. Primary onsite focal point for malfunctions in thermal liquid cooling stations. Diagnose and resolve hardware/software issues to maintain continuous development labs activity Maintain and update hardware (manifolds, connectors, sensors) and software versions across all thermal systems according to engineering specifications. Perform initial RCA on thermal system failures. Extract detailed fail reports and corrective/

At Lyft, our purpose is to serve and connect. We aim to achieve this by cultivating a work environment where all team members belong and have the opportunity to thrive. Flexdrive is a subsidiary of Lyft that works together with Lyft teams to realize our shared mission. Flexdrive builds the operational backbone for the future of mobility. As a fleet management leader and Lyft subsidiary, the company extends its expertise into autonomous vehicle infrastructure — managing the physical operations that keep fleets safe, available, and performing at scale. The Nashville depot is the first proof point in a multi-market expansion. The Opportunity Reporting to the Operations Manager, AV Depot, the Associate Operations Manager is the second leadership layer at the Nashville AV depot. This role exists because one Operations Manager cannot provide the people leadership, floor coverage, and operational bandwidth a 24/7 depot of this scale requires. The Associate Operations Manager carries ownership across two critical business workstreams: workforce scheduling support and process standards compliance. Fleet Operations Leads report to the Operations Manager — but during mid shifts, the Associate Operations Manager is the operational authority on the floor, directing their work, setting the quality standard, and serving as their most experienced resource and mentor. This is a management role with a floor orientation. The Associate Operations Manager is present, coaching, directing, and executing alongside the team — while simultaneously carrying business responsibilities that directly impact depot readiness and partner compliance. This role is the bridge between the Fleet Operations Lead layer and the Operations Manager. Responsibilities: Scheduling & Workforce Planning Support Owns the depot schedule — building, maintaining, and adjusting shift coverage across all teams to ensure the depot is consistently staffed and operationally ready. Monitors attendance, manages rea

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a key technical contributor within the High Bandwidth Memory (HBM) Product Engineering – Media Health team, you will play a critical role in driving Media Health manufacturing execution for Micron’s latest next‑generation HBM products, including DRAM die, interface die, and stacked HBM solutions. You will be responsible for Best‑in‑Class HBM product enablement, with direct technical ownership across the core manufacturing KPIs of Quality, Cost, Cycle Time, and Scale. Your contributions will include manufacturing test flow development and validation, device‑ and stack‑level yield improvement, and delivery of optimized extrinsic and intrinsic reliability through deep circuit debug, test coverage optimization, and innovative test strategies. In this role, you will drive manufacturing test time reduction, enhance overall manufacturing efficiency, and contribute to Design‑For‑Test (DFT) strategy development, introducing new ideas that improve cost competitiveness, cycle time, and product quality. You will work closely with cross‑functional partners—including Fab, Product Leads, Design Engineering, Technology Development, and Test Solutions Engineering—to execute both strategic initiatives and tactical deliverables, ensuring continued technology and product leadership. The future of HBM is fast‑moving and

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. About the Role As a Member of Technical Staff (MTS) in Micron’s HBM Product Engineering Component Validation team, you will serve as a technical leader and authority for the validation of advanced High Bandwidth Memory (HBM) products. You will apply deep DRAM and HBM architecture and design knowledge to define validation coverage strategy, lead complex product debug and failure analysis, and drive a zero-escape validation mindset across all test modes and product milestones. Operating within Micron’s global validation organization and partnering closely with teams across multiple sites, you will influence design-intent-to-coverage decisions, mentor engineers, and set the technical direction for current and next-generation HBM validation. Responsibilities and Tasks Technical Leadership & Validation Strategy Act as a technical authority for HBM Component Validation, translating DRAM/HBM design intent and architecture into comprehensive validation coverage and test strategy. Define and own validation methodologies and coverage plans across structural (black-box) and functional test flows, driving toward full validation coverage at each product milestone with zero validation escapes. Lead validation definition and closure for new and high-risk product

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Implement and integrate DFT logic at block, s

Job Details: Job Description: Join our Communication Runtimes team as a Senior Cloud Software Development Engineer to develop cutting-edge software features and optimizations for Intel's oneCCL (Collective Communications Library). This role offers the opportunity to build expertise with the latest Intel GPUs and CPUs used in data centers, collaborate directly with scientists and engineers on the Aurora supercomputer at Argonne National Labs, and make meaningful contributions that advance scientific computing and machine learning capabilities. Key Responsibilities Communication Library Development Design, develop, and maintain advanced features and performance optimizations for oneCCL. Optimize software to achieve performance requirements including low latency, high bandwidth, and high reliability Implement and enhance communication protocols across multiple layers of the communications stack Cross-Functional Collaboration and Requirements Collaborate with cross-functional teams to define software requirements and technical specifications Work directly with scientists and engineers on high-performance computing applications and supercomputer implementations Partner with hardware teams to optimize software-hardware integration for maximum performance Performance Optimization and Analysis Develop performance optimizations that improve communication latency and throughput Conduct comprehensive performance analysis and benchmarking across different system configurations Debug complex problems spanning multiple layers of hardware and software stack What You'll Work On Aurora Supercomputer: Direct collaboration with Argonne National Labs on one of the world's

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.

About the Team DoorDash Labs is DoorDash's autonomous delivery group, building the robots and hardware that move goods without a driver. The Hardware team designs the electronics at the core of these systems — digital and mixed-signal control boards, power and motor-control electronics, embedded firmware, and the test and integration benches that prove the whole system works. We're building out an experienced and diverse set of electrical engineers to increase our velocity, bandwidth, and operations. About the Role You'll bring PCB layout in-house — a core quality goal — owning floorplanning, stackups, and layout while coordinating closely with mechanical, thermal, and SI/PI engineering to land complete, manufacturable boards. You will report into the Director, Electrical Engineering on our Hardware team in our DoorDash Labs organization. Our offices are open, and depending on the role this position is hybrid or fully onsite — expect to be fully onsite when needed. You're excited about this opportunity because you will… Perform floorplan analysis and create stackups, layout, and footprints Work with mechanical engineering to ensure fit and form compatibility with mechanical systems Work with thermal engineering to ensure a thermally sound layout Work with SI/PI engineering to ensure the board design is complete and robust Drive toward consistently high-quality layout We're excited about you because… Strong PCB layout experience across digital and mixed-signal boards Familiar with stackup technologies, their limitations and considerations, and cost/lead-time impacts Controlled-impedance and high-speed routing know-how; PI/PDN fundamentals Proficient in a professional layout tool (Altium, Cadence, or similar) Comfortable coordinating with mechanical, thermal, and SI/PI engineering Compensation The successful candidate’s starting pay will fall within the pay range listed below and is determined based on job-related factors including, but not limited to, skills, experie

About the Team DoorDash Labs is DoorDash's autonomous delivery group, building the robots and hardware that move goods without a driver. The Hardware team designs the electronics at the core of these systems — digital and mixed-signal control boards, power and motor-control electronics, embedded firmware, and the test and integration benches that prove the whole system works. We're building out an experienced and diverse set of electrical engineers to increase our velocity, bandwidth, and operations. About the Role You'll own mixed-signal and analog design — a key capability gap for the team — and raise the analog bar across our control hardware, from instrumentation and telemetry to sensor interfaces and precision analog. You will report into the Director, Electrical Engineering on our Hardware team in our DoorDash Labs organization. Our offices are open, and depending on the role this position is hybrid or fully onsite — expect to be fully onsite when needed. You're excited about this opportunity because you will… Design instrumentation and telemetry-measurement circuits, precision current sources, and high-quality amplifiers Design circuits around ADCs, DACs, and signal conditioning Design sensor interfaces — temperature, light, audio — and LED drivers Own power sequencing and EMC-aware analog design Bring analog rigor to design reviews and help set analog/EMC design practices We're excited about you because… Strong mixed-signal and precision-analog design background Instrumentation, telemetry, current-source, and power-amplifier design ADC/DAC and signal-conditioning design; sensor front-ends (temp/light/audio) and LED drivers EMC/EMI-aware design and mitigation experience You characterize analog performance in the lab (noise, bandwidth, accuracy) Compensation The successful candidate’s starting pay will fall within the pay range listed below and is determined based on job-related factors including, but not limited to, skills, experience, qualifications, work lo

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. In HBM HIG (High Bandwidth Memory, Heterogeneous Integration Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and testing (validation) of HBM is the most ambitious due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, the

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Within Micron’s Heterogeneous Integration Group (HIG), we are developing advanced High Bandwidth Memory (HBM) solutions that enable the next generation of AI, high-performance computing, and data-centric applications. Our team collaborates across design, product, manufacturing, and ecosystem partners to deliver innovative memory technologies with exceptional quality and execution excellence. The HBM Tapeout and Release Technical Lead plays a critical role in ensuring successful design releases into Micron manufacturing. In this role, you will drive tapeout execution, release readiness, and design governance across complex HBM programs, partnering with design, integration, verification, and product teams to deliver high-quality designs on schedule. Responsibilities: Lead tapeout execution and release coordination for HBM builds, managing schedules, DBR achievements, and release readiness Drive preparation, review, and completion of tapeout collateral, including TOAST, RCDB, TWIT, and related release documentation Coordinate signoff readiness across timing, power, physical verification, integration, and other release-critical activities Ensure database quality, completeness, traceability, and signoff evidence are in place prior to tapeout Manage release risks, waivers, open items, and governance processes while maintaining strong r