Band6 Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Within Micron’s Heterogeneous Integration Group (HIG), we are driving the next generation of High Bandwidth Memory (HBM) solutions that power advanced computing and AI applications. Our team brings together experts across design, product development, manufacturing, and ecosystem partnerships to solve complex technical challenges and deliver innovative memory technologies. The Design Development Technical Lead (DDTL) plays a critical role in enabling predictable, high-quality execution across the HBM design lifecycle. As the single-threaded technical program owner for HBM Build, you will coordinate cross-functional teams. You will manage technical dependencies and risks. You will provide clear leadership across build, product, and executive collaborators to ensure successful program delivery. Responsibilities: Lead end-to-end execution of HBM build achievements across DRAM, base die, test vehicles, interposers, IP, and sustaining development efforts Drive multi-functional alignment, manage dependencies, and maintain execution plans to achieve schedule, cost, and quality objectives Lead governance activities including design reviews, program reviews, risk management, and change control processes Partner with foundries, IP vendors, contractors, and procurement teams to resolve execution challenges and support design delivery Own roadmap communication, executive reporting, and collaborator alignment for HBM build programs Minimum Qualifications: Bachelor’s degree in Electri

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has transformed innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are redefining how the world uses information to enrich life. We are looking for Layout Build engineer at our Micron Technology’s DRAM Team in Guadalajara, Mexico. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Responsibilities: Build and development of analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for timely delivery of block-level layouts with acceptable quality. Will bee leading planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. Optimally copresentingith Global engineering teams to assure the success of layout project. Minimum Qualification: Around 5 years of experience in analog/custom layout design in sophisticated CMOS process, in various technology nodes (Planar, FinFET). <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will contribute to the design and delivery of next‑generation memory products by working across circuit design, layout, and validation. You will apply simulation, modeling, and verification skills to improve

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. Micron is seeking a Design Infrastructure Engineer to build, enable, and scale characterization infrastructure and deliver generated IP to multiple advanced memory and logic developments. This position includes characterizing both standard and custom cells across various process technologies. These encompass Micron internal nodes as well as external foundries, such as TSMC. The position supports multiple HBM product lines, including HBM DRAM dies, Logic dies (JEDEC and custom variants), and advanced 3D HBM architectures. You will work where circuit build, EDA infrastructure, and silicon validation readiness meet. You will develop robust, scalable, and high-quality characterization flows. These flows directly affect timing closure, power modeling, and product quality for next-generation HBM programs. Responsibilities: Develop and sustain scalable infrastructure for standard cell and custom cell characterization, encompassing timing, power, noise, and signal integrity modeling. Build reusable, a

About the Job: Feature management and experimentation have converged into a single market, and the buying dynamic at the top has shifted. Engineering teams are no longer the sole evaluator — data scientists and data-focused PMs now carry equal weight on the largest deals. The bar for statistical depth, warehouse ergonomics, and experiment-first workflows is rising quickly. In traditional experimentation we have built the foundation: a trusted runtime control plane, a growing experimentation engine, and early warehouse-native capabilities. We are winning lower-maturity buyers at healthy rates. We are not yet consistently winning the most sophisticated data organizations. Closing that gap is the job. In AI experimentation, we have an early lead: the AI-native tooling category has invested in evaluation and conceded production experimentation, and we already have the primitives (statistical significance, multi-armed bandits, experiment-aware guardrails) that no AI-native competitor ships. Extending that lead is the other half of the job. This leader will own whether LaunchDarkly becomes the definitive experimentation platform in an AI-accelerated world. Responsibilities: Own the Experimentation pillar. Direct leadership of the Product team. Partner with Engineering and Design counterparts in a triad model. Accountable for the pillar's strategy, roadmap delivery, and commercial outcomes. Make the investment case across the in-product experimentation experience, the warehouse-native analysis layer, and the infrastructure that scales them. Make experimentation the measurement layer of the AI SDLC. Partner with our AI product, observability, and core feature management leaders to productize the capabilities we already have as AI-native primitives. Build a closed loop from offline evaluation through production experiments, to automatic promotion and rollback, to a self-improving feedback loop for agents. Win the high-maturity buyer. Earn the technical confidence of senior d

OVERVIEW Warehouse and Day Operations responsibilities: The Warehouse Picker/Receiver is expected to lead by example and ensure all projects and day to day work is performed in accordance with company standards. This position is expected to work closely with the Tile Warehouse Manager on a daily basis. A warehouse Picker/ Receiver is both a receiver and a picker tasked with loading and unloading of inbound/outbound trucks in a timely manner. Organizing and putting away material in designated locations. Communicate all discovered or suspected material damage or inventory issues to the Tile Warehouse Manager. Pulling/compiling customer orders onto consolidated pallets. Wrapping up and banding pallets after being put together to ensure safe delivery. Loading and Unloading trucks. Aid in customer pickups where material is expected to be safely put into residential vehicles. Work together with coworkers to pull large and awkward boxes and pieces. This position will assist in the container receipt process including physically unloading materials & making system inputs. Work with the operations team on all projects that aid in the improvement and advancement of our overall operations. Maintain a safe and clean work area. Job Requirements: Availability to work Monday – Friday during the window of 7:30 am - 5:00 pm. The ability to regularly lift and move heavy boxes 50-75 lbs. Knowledge and experience with forklifts and reach machines required. At least 1-year prior experience. Must have reliable transportation to get to and from work. Must be able to stand for long periods of time. BENEFITS Medical Dental Vision Employer Paid Basic Employee Life and AD&D Insurance Employer Paid Long Term Disability Flexible Spending Accounts Voluntary Short-Term Disability Voluntary Life and AD&D Insurance Voluntary Accident Insurance Voluntary Critical Illness Insurance EEO At Construction Resources, our people are the driving force be

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. At Micron, we believe in encouraging a culture of innovation and excellence. The PDE Process Integration (PI) Senior Manager role offers an outstanding chance to lead a distributed team in defining, standardizing, and driving High Bandwidth Memory (HBM) New Product Introduction (NPI) success across several locations. This position blends strategic leadership, scaling of operations, and coordination across sites. It aims to ensure consistent PI readiness, faster yield ramp, and strong risk management from development through High Volume Manufacturing (HVM). Job Responsibilities Define and drive PI strategy, standards, and guidelines across HBM programs. Coordinate PI execution across multiple HBM NPI programs, ensuring delivery against network-level achievements and ramp targets. Ensure robust risk identification, early detection mechanisms, and mitigation strategies. Serve as the central PI leader collaborating with various engineering and manufacturing organizations. Champion the adoption of AI-enabled tools for yield analysis and risk prediction. Organizational Leadership & Talent Strategy Guide and grow a group of PI managers and senior engineers spanning several locations or departments.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever ! The Heterogeneous Integration Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications. Using Through Silicon Via (TSV) technology, we stack multiple DRAM chips with a high-speed interface die, significantly increasing memory density and bandwidth for next-generation AI/ML accelerators and high-performance computing platforms. Our designs target the industry's lowest power-per-bit and highest bandwidth, enabling the most demanding compute workloads. We are seeking a SI/PI Engineer in HBM Build Architecture to develop high-quality SI/PI analysis for interposers, packages, and silicon channels. This work contributes directly to HBM build sign-off and product success. You will be involved in complex, multi-disciplinary SI/PI initiatives spanning multiple HBM product generations — from early interposer channel analysis and equalization co-design, PDN architecture, and system PI analysis. You will ensure Micron's HBM SI/PI architecture remains the industry benchmark for signal quality, power delivery integrity, and interface reliability. This role supports the design and deployment of AI-enabled solutions that improv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As MSH PDE Yield Enhancement (YE) Lead Engineer within Package Development Engineering (PDE), you will lead a team of YE Engineers responsible for yield performance, excursion management, and yield stabilization across High Bandwidth Memory (HBM) New Product Introduction (NPI) . This role is accountable for ensuring predictable yield ramps , fast learning closure , and robust manufacturing readiness for advanced HBM technologies. You will provide people leadership, technical direction, and execution governance , partnering closely with Process Integration (PI), MRDA, Process Engineering, Assembly/Test Manufacturing, Quality, and Program Leadership to protect schedule, yield, and customer commitments. Job Responsibilities People & Team Leadership Build, lead, and develop a high‑performing MSH PDE YE team Set clear expectations on yield ownership, execution discipline, and escalation behavior Coach engineers on technical rigor, structured problem solving, and stakeholder communication Drive individual development plans, succession planning, and technical depth within the YE team Ensure sustainable on‑call / coverage models for critical NPI and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal IO/Clocking Design Engineer to be a part of our design team working on critical high-speed circuits common to all DRAM related memory products! In this position, you will be responsible for the development, design, optimization, verification, and fan out of these high-speed circuits to all DRAM related projects at Micron. You will work on equalization and bandwidth extension to push the speed limits of the circuit and process technology, analyze resulting IO impairments, clock jitter and duty error impact to DRAM system and timing budget, and develop effective engineering solutions. Responsibilities: Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply proven high-speed circuit design techniques and enhance critical performance evaluation of the IO data path and clocking path at circuit level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities. Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node. Minimum Qualifications: Minimum MSEE &#43; 10 years or BSEE &#43; 12 years of industry experience in analog and mixed-signal circuit design. Proficiency w

OVERVIEW Warehouse and Day Operations responsibilities: The Warehouse Picker/Receiver is expected to lead by example and ensure all projects and day to day work is performed in accordance with company standards. This position is expected to work closely with the Tile Warehouse Manager on a daily basis. A warehouse Picker/ Receiver is both a receiver and a picker tasked with loading and unloading of inbound/outbound trucks in a timely manner. Organizing and putting away material in designated locations. Communicate all discovered or suspected material damage or inventory issues to the Tile Warehouse Manager. Pulling/compiling customer orders onto consolidated pallets. Wrapping up and banding pallets after being put together to ensure safe delivery. Loading and Unloading trucks. Aid in customer pickups where material is expected to be safely put into residential vehicles. Work together with coworkers to pull large and awkward boxes and pieces. This position will assist in the container receipt process including physically unloading materials & making system inputs. Work with the operations team on all projects that aid in the improvement and advancement of our overall operations. Maintain a safe and clean work area. Job Requirements: Availability to work Monday – Friday during the window of 7:30 am - 5:00 pm. The ability to lift and move heavy boxes 50-75 lbs. Regularly. Knowledge and experience with forklifts and reach machines required. At least 1-year prior experience. Must have reliable transportation to get to and from work. Must be able to stand for long periods of time. BENEFITS Medical Dental Vision Employer Paid Basic Employee Life and AD&D Insurance Employer Paid Long Term Disability Flexible Spending Accounts Voluntary Short-Term Disability Voluntary Life and AD&D Insurance Voluntary Accident Insurance Voluntary Critical Illness Insurance EEO At Construction Resources, our people are the driving force behind e

What We’re Looking For: We’re looking for an XPU Architect to own the XPU compute engine architecture of the A-0 and A-1 systems. This will initially involve heavily leveraging existing 3rd party IP, but in a creative way to solve the bandwidth demand challenges and memory system interface challenges. Future generations of the compute XPU will be semi-custom and custom designs. Ideal Background: An ideal candidate will have: Previous experience architecting and owning a high performance, high TDP ASIC (eg AI chips, network switch chips, high performance CPUs or similar) Knowledge of both computer architecture but also silicon implementation, and understanding of the realistic constraints that silicon implementation places upon architectural options Deep understanding of AI workloads, especially low latency LLM inference Understanding of workload and system level bottlenecks, especially around inference, as it pertains to interconnect, memory capacity, bandwidth, latency, etc. Strongly Preferred: Hands-on experience with AI chip architecture and tapeouts End to end ownership of at least one AI ASIC project History of product delivery (regardless of ultimate commercial success of said product) Experience with HBM-based AI chip architecture Experience in proposing “weird” chip architectures (in any domain, not just AI!)

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. What’s Encouraged Daily: Contribute to the development of new HBM products by assisting with the overall design, and layout. · Interpret product specifications and design circuits to meet the required functionality. · Design, implementation, and improvement of Complex Analog Mixed Circuits such as CMOS Amplifiers, Comparators, Bandgap references, V2I converters, LDOs, charge pumps, Oscillators , DLL, IO circuits (DDR/LPDDR), Delays, Process and temperature sensors in advanced semiconductor process nodes for advanced High Bandwidth Memory ( HBM ) products · Integration of modules with Power delivery network and propose design solution for optimum performance · Deep understanding of Array and its peripheral circuits. · Driving innovation into the future Memory generations within a dynamic work environment · Validate & optimize design for reliability (Device stress, Aging effect) · EM/IR simulation, optimize layout to achieve best circuit performance ·

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Design, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products. Design, implementation and integration of synchronous and asynchronous custom digital block Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits. Parasitic modeling and design validation, reticle experiments and required tape-out revisions. Overseeing and managing the layout process including floor-planning, placement, and routing Performing verification processes with modeling and simulation using industry standard simulators Contributing to cross group communication to work towards standardization and group success. Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product. Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality. Mentor and lead young designers. Usage & working with AI Skills is must Strong

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Design, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products. Design, implementation and integration of synchronous and asynchronous custom digital block Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits. Parasitic modeling and design validation, reticle experiments and required tape-out revisions. Overseeing and managing the layout process including floor-planning, placement, and routing Performing verification processes with modeling and simulation using industry standard simulators Contributing to cross group communication to work towards standardization and group success. Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product. Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality. Mentor and lead young designers. Usage & working with AI Skills is must Strong