Design Manager Jobs

Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE) — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Principal, IO Design Engineering — Boise, ID - Main Site. Apply via Workday.

Principal Engineer, Project Design Verification Lead — Hyderabad - Phoenix Aquila, India. Apply via Workday.

ENGINEER, SIG ELECTRICAL DESIGN — Boise, ID - SIG Building. Apply via Workday.

Sr Engineer, Design — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Be part of a highly skilled and challenging high-speed PHY design team working on advanced technology nodes (12nm and below). Own analog sub-blocks within the PHY and drive specification, design, simulation, reliability, and mixed-mode verification. Leverage AI-enabled tools to improve productivity and decision-making. Drive layout implementation through mask designers while ensuring compliance with process rules and DFM requirements. Participate in design reviews with internal teams and customers, explaining design choices and robustness. Collaborate with cross-functional teams across multiple global locations. Create IP EDA views including Behavioral models, Verilog-A, timing views, and abstracts. Participate in silicon bring-up, characterization, and correlation of silicon results with models and simulations. Mentor and guide junior engineers. Competitive compensation and equal opportunity workplace. Required Skills Strong analog/mixed-signal CMOS circuit design experience in deep sub-micron technologies (2nm to 28nm). Experience in High-Speed Memory Interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA, etc.). Full ownership experience of at least one critical PHY sub-block such as: PLL DLL CDR High-speed Receiver with Equalization Transmitter Front-End High-Speed Data Path </ul

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Contribute to the development of new product opportunities by assisting with the overall Verification Activities of DRAM Design Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate verification cycle time Assist in Test-Case/TB and various other components required for DRAM Design Verification Improve debug efficiency across simulation and silicon learning loops Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features Develop and maintain test benches / test vectors using simulation tools and run regressions for coverage analysis and improvements using Agentic AI Flow Participate in simulating, analyzing, and debugging pre-silicon full chip designs by applying leading edge verification technique Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environ

PRINCIPAL ENGINEER, DDEG DESIGN METHOD — Hyderabad - Phoenix Aquila, India. Apply via Workday.

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role As an AV Engineer focused on builds and design, you'll design and implement the systems that enable world-class collaboration and communication across offices. This role is critical as we rapidly expand our physical footprint, with plans for multiple new offices and expansions over the coming years. You'll be responsible for architecting AV solutions from concept through commissioning, ensuring our conference rooms, event spaces, and collaboration areas provide frictionless experiences that enable our teams to advance AI safety research. You'll help establish standards and systems that scale efficiently while pushing the boundaries of what's possible in workplace collaboration technology. This is an opportunity to shape how a cutting-edge AI research organization communicates and collaborates, building infrastructure that supports everything from small team meetings to company-wide all-hands broadcasts reaching thousands of remote participants. Responsibilities Lead AV design, procurement, and programming for new office builds, expansions, and retrofits across our global portfolio Create and maintain AV system designs including schematic drawings, line diagrams, and elevation plans Program and commission AV systems to meet specific use cases and user requirements Execute successful "first day of business" deployments for new offices, ensuring all systems are operational for day-one occupancy Attend build coordination meetings with architects, contractors, and workplace teams to drive AV requirements and integration Innovate and test emerging AV technologies to optimize productivity and enable premium experiences for exi

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role As an AV Engineer focused on builds and design, you'll design and implement the systems that enable world-class collaboration and communication across offices. This role is critical as we rapidly expand our physical footprint, with plans for multiple new offices and expansions over the coming years. You'll be responsible for architecting AV solutions from concept through commissioning, ensuring our conference rooms, event spaces, and collaboration areas provide frictionless experiences that enable our teams to advance AI safety research. You'll help establish standards and systems that scale efficiently while pushing the boundaries of what's possible in workplace collaboration technology. This is an opportunity to shape how a cutting-edge AI research organization communicates and collaborates, building infrastructure that supports everything from small team meetings to company-wide all-hands broadcasts reaching thousands of remote participants. Responsibilities Lead AV design, procurement, and programming for new office builds, expansions, and retrofits across our global portfolio Create and maintain AV system designs including schematic drawings, line diagrams, and elevation plans Program and commission AV systems to meet specific use cases and user requirements Execute successful "first day of business" deployments for new offices, ensuring all systems are operational for day-one occupancy Attend build coordination meetings with architects, contractors, and workplace teams to drive AV requirements and integration Innovate and test emerging AV technologies to optimize productivity and enable premium experiences for exi

Perplexity is looking for a frontend engineer to build the design system behind every Perplexity product. It is the component library and design language shared across web, iOS, Android, macOS, and Windows – the primitives, tokens, and interaction patterns that every product team builds on top of. Its users are internal, spanning product teams and a broad range of contributors across the company. The components you build become the foundation all of them rely on. You will develop component APIs that hold up across dozens of consuming surfaces and are easy for other teams to adopt correctly, contribute to the token pipeline that keeps five platforms visually consistent, and maintain a high bar for interaction quality and accessibility. Tech Stack: React · TypeScript · CSS · Design Tokens What you'll do Design and build core primitives – overlays, inputs, navigation, feedback – with APIs that stay coherent as consumers multiply Work across the design-token pipeline – authoring, generation, and per-platform publishing across web, iOS, Android, macOS, and Windows Partner directly with design on the design language itself, translating Figma systems into typed, testable, documented components Migrate product surfaces off bespoke implementations onto shared primitives without breaking them Build accessible components by default – keyboard, focus, contrast, screen readers – backed by automated coverage Support consuming teams through docs, visual regression coverage, and on-call rotation What we're looking for 4+ years building production frontend; experience with a design system, component library, or shared UI platform is a plus Interest in building reusable components Strong React and TypeScript, and CSS Working accessibility knowledge (WCAG, ARIA patterns, assistive tech) Comfort collaborating closely with designers on the visual and interaction language

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence. You will turn evolving architecture and design needs into reusable tools and workflows that improve iteration speed, quality, and then apply those tools to help construct world-class silicon. You’ll work closely across architecture, design, verification, performance modeling, and systems software. This role is well suited for an engineer who enjoys building high quality software and is motivated by the challenge of improving velocity and quality of the silicon development process. In this role, you will: Develop and scale design methodologies for rapid first-party chip development and apply them to construct complex custom chips Create abstractions that allow hardware structures, configurations, experiments, and results to be represented consistently across tools. Automate high-value engineering workflows and improve their reproducibility, observability, testability, and ease of use. Partner with architects, RTL designers, verification engineers, compiler engineers, and systems software engineers to gather requirements and then implement solutions. Use methodology and tooling to identify design risks early, accelerate iteration, and improve confidence in performance and implementation tradeoffs. Contribute across multiple aspects of software and hardware

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s DRAM Design Engineering Group (DDEG) is where bold ideas become real technology. We push the limits of memory and storage innovation, and we thrive in a collaborative environment where engineers learn, build, and solve challenges together. We are driven by curiosity, creativity, and the pursuit of better solutions every day! We are seeking a Principal or Member of Technical Staff (MTS) in Analog Design to join our DRAM IP Design team. As a Principal/ MTS, you will help shape the next generation of Micron's memory products, while working closely with global design, verification, and product teams to bring innovative circuit designs from concept to silicon. Your work will directly influence product performance, quality, and reliability—and contribute to advancements that define the semiconductor industry. Responsibilities: Design, optimize, and verify block‑level analog and mixed-signal circuits for DRAM projects. Work with the internal data science team and EDA vendors to leverage Agentic- AI and improve AI-assisted design flow and circuits optimization. Propose, evaluate and implement new or improved circuit topology to further enhance PPAC of the circuit block. Improve design verification scope and coverage to increase circuit robustness to enhance mass production yield. Partner with global design groups and provide layout guidance through post‑layout simulation. Com

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal IO/Clocking Design Engineer to be a part of our design team working on critical high-speed circuits common to all DRAM related memory products! In this position, you will be responsible for the development, design, optimization, verification, and fan out of these high-speed circuits to all DRAM related projects at Micron. You will work on equalization and bandwidth extension to push the speed limits of the circuit and process technology, analyze resulting IO impairments, clock jitter and duty error impact to DRAM system and timing budget, and develop effective engineering solutions. Responsibilities: Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply proven high-speed circuit design techniques and enhance critical performance evaluation of the IO data path and clocking path at circuit level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities. Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node. Minimum Qualifications: Minimum MSEE &#43; 10 years or BSEE &#43; 12 years of industry experience in analog and mixed-signal circuit design. Proficiency w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building the next generation of solid‑state drive controllers at Micron, where cutting‑edge ASIC design meets high‑performance storage innovation. Our team works across the full silicon lifecycle, partnering closely with verification, physical design, and system teams to bring complex designs to life. If you enjoy solving deep technical challenges and collaborating with experts across disciplines, this is an exciting place to make an impact! In this role, you will play a key part in delivering advanced ASIC designs from concept through production silicon. You will define micro‑architectures, develop RTL, and ensure designs meet performance, timing, and quality goals. This position offers strong ownership, collaboration, and the opportunity to leverage modern AI‑assisted tools to improve engineering efficiency and quality. Responsibilities: Design, implement, and debug complex RTL logic and integrate IP into larger subsystems Support front-end design flow including lint, CDC, synthesis, and ECO activities Collaborate with SOC design, verification, STA, and physical design teams to deliver high-quality silicon Develop automation scripts to improve design efficiency and productivity Use AI-assisted tools to enhance debugging, documentation, and code quality Minimum Qualifications: MS in Electrical Engineering or equivalent e