Design Verification Engineer Intern Jobs

The NVIDIA DGXC Data Services team builds cloud-native systems, frameworks, and services for managing data across hybrid and multi-cloud infrastructure. We are building the next-generation data and storage infrastructure to solve some of the hardest problems in AI: storage, access, ingestion, governance, observability, and data management for exabyte-scale, high-performance GPU-based training and inference jobs. Our work gives NVIDIA teams the foundational capabilities they need to build, train, deploy, and operate AI products at scale without reinventing critical data infrastructure for every workload. What you will be doing: Build storage technologies, client libraries, and filesystem frameworks that help AI workloads access data across object stores, file systems, and hybrid cloud infrastructure. Develop high-performance storage paths for training and inference workflows, including data loading, checkpointing, caching, POSIX-style access, and object-store integration. Build observability systems that diagnose storage bottlenecks, attribute GPU idle time to I/O behavior, and expose actionable telemetry through production monitoring stacks. Improve performance, scalability, and reliability of storage systems serving massive datasets, deep directory trees, and high-concurrency AI workloads. Work closely with internal AI teams, platform teams, SRE, and operations to validate storage behavior against real workloads and production environments. Use modern software engineering practices, including AI-assisted and agentic development workflows, while maintaining high standards for design, testing, security, performance, and verification. What we need to see: BS in Computer Science, Information Sys

Electro-Optical/Infrared Signature Analyst Engineer (Mid-Level or Senior) Company: The Boeing Company The Boeing Defense, Space & Security (BDS) - Phantom Works organization is seeking an Electro-Optical/Infrared Signature Analyst Engineer (Mid-Level or Senior) to join the Phantom Works team located in St. Louis, MO. This is a great opportunity to work on new systems and technologies as part of an integrated product team. This position will apply knowledge of advanced infrared and electro-optical signature design, analysis, integration, and test techniques for system integration. Candidates will apply electromagnetic theories and principles to develop new and innovative systems and components for next generation platforms. This job requires both hands-on and deskwork. Position Responsibilities: Perform design, analysis, and integration activities for technology and design integration of EO/IR design practices into advanced platforms Assist in developing and documenting requirements for electromagnetic systems and components Perform modeling and simulation of EO/IR performance for design optimization and validation Generate design influence initiatives and direct design trade studies that may result from those initiatives Work with suppliers and customers (internal and external) to ensure compliance, verification, and validation with technical requirements Support and execute test plans and validation activities (lab and range) to verify performance and support correlation between simulation and measurement Collaborate with multidisciplinary teams (structures, propulsion, materials, flight test, systems engineering, producibility) to ensure integrated soluti

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Design and maintain standard cells layout for new DRAM products on new technology Lead the stdcells layout projects from initial spec definition to till PPA qualified library release Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Perform layout verification like LVS/DRC/Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Develop new flows/methodologies to reduce the stdcells manual effort & increase the productivity Closely work with the Process team, CMOS and CAD to negotiate drc for new technology. Co-work with international colleagues on developing new flows and tools for stdcells layout & design Leverage AI tools to automate the tools and workflow Use AI-assisted workflows to improve design productivity About Micron Technology, Inc. We a

The NVIDIA DGXC Data Services team builds cloud-native systems, frameworks, and services for managing data across hybrid and multi-cloud infrastructure. We are building the next-generation data and storage infrastructure to solve some of the hardest problems in AI: storage, access, ingestion, governance, observability, and data management for exabyte-scale, high-performance GPU-based training and inference jobs. Our work gives NVIDIA teams the foundational capabilities they need to build, train, deploy, and operate AI products at scale without reinventing critical data infrastructure for every workload. What you will be doing: Build cloud-native data and storage services for hybrid and multi-cloud infrastructure, including dataset discovery, ingestion, governance, checkpointing, observability, and low-latency access. Develop scalable cloud-native services and APIs that support exabyte-scale, high-performance GPU training and inference workflows. Work closely with product managers, internal AI teams, platform teams, and partner engineering teams to understand requirements and turn them into reliable production systems. Collaborate with SRE, operations, and support teams to improve service reliability, performance, observability, on-call readiness, and operational scale. Use modern software engineering practices, including AI-assisted and agentic development workflows, while maintaining high standards for design, testing, security, and verification. What we need to see: BS in Computer Science, Information Systems, Computer Engineering, or equivalent experience, with 5+ years of software engineering experience. Strong foundation in algorithms, data structures, distributed systems, and practi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are hiring a Layout Engineer for Micron Technology’s HBM Team in Hyderabad, India. In this role, you will contribute to advanced applications including artificial intelligence and high-performance computing solutions with High Bandwidth Memory. You will coordinate with peer groups across Micron's worldwide locations on multiple projects, providing an exceptional chance for career development! Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership qualities in area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environments. • Ability to guide Peer team-members in their execution of Sub block-level layouts & review critical items. • Effectively communicating with Local engineering teams to assure the success of layout project

Zeal is an AI-enabled software consultancy purpose-built for Fortune 1000 companies, and we’re now part of Livefront . We help companies navigate technology to drive business outcomes by attracting, retaining, and growing exceptional talent and empowering them to use innovative technologies and process frameworks. We’re a values-driven technology company grounded in kindness, generosity, and integrity. Our mission is to build a place where our employees love their future and where clients trust us to deliver what we promise: to improve their business through technology. Love your future. We’re looking for an outstanding Java Engineer to join our team. This role is available across our primary LATAM hub in Peru. Who you are You are a pragmatic problem-solver who enjoys turning complex business challenges into effective, high-quality technology solutions. You communicate clearly with both clients and technical peers, you adapt easily across industries and technical stacks, and you have a keen interest in consulting. You are curious about new tools—including AI tools that improve your productivity. What you will be doing Work directly with clients to analyze business problems and implement technology solutions. Develop software, design solutions, and collaborate with senior consultants to deliver high-quality outcomes. Learn and apply best practices in software engineering, cloud technologies, and system architecture. Gain experience across multiple clients and industries, adapting to different technical and business environments. Build trust with clients and internal teams through strong communication, problem-solving, and execution. Execute custom software development, primarily utilizing established languages and frameworks, including: C#, Entity Framework, ASP.NET, Java, Spring Boot, and Python; JavaScript, TypeScript, React, Angular, Next.js, .NET MAUI, Flutter, and Xamarin. Implement automated verification protocols for software systems to ensure operationa

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are hiring a Layout Engineer for Micron Technology’s HBM Team in Hyderabad, India. In this role, you will contribute to advanced applications including artificial intelligence and high-performance computing solutions with High Bandwidth Memory. You will coordinate with peer groups across Micron's worldwide locations on multiple projects, providing an exceptional chance for career development! Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership qualities in area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environments. • Ability to guide Peer team-members in their execution of Sub block-level layouts & review critical items. • Effectively communicating with Local engineering teams to assure the success of layout project

Mid-Level or Senior Aerospace Systems Safety Engineer Company: The Boeing Company The Boeing Defense Air Dominance Division Systems Safety & Mission Assurance organization is looking for an Aerospace Systems Safety Engineer to join our team in Hazelwood, MO . Our teams are currently hiring for a broad range of experience levels including Experienced (Level 3) or Senior (Level 4) Aircraft Safety Engineers. A successful candidate will perform system software safety engineering work on a Proprietary Air Dominance program, drive hazard analyses, demonstrate compliance to MIL‑STD‑882E and other standards, and influence system architecture to reduce safety risk. The selected candidate will provide technical guidance and perform critical Software System Safety Engineering work. In addition to working with System Safety personnel, the individual will work extensively with design, development, and test to incorporate robust safety features and reduce project safety risk. Primary responsibilities: Analyzes the integration of complex airplane systems and their corresponding airplane-level effects, failure indications, and flight crew actions as part of a system of systems analysis Documents safety analyses, hazard mitigation, validation, and verification activities in compliance with relevant customer and regulatory safety standards such as MIL-STD-882E, MIL-HDBK-516C, AC-17-01, DO-178C, and DO-254. Demonstrates safety hazard risk mitigation and control methods to the customer and regulators Identifies safety issue systemic root causes and recommends corrective actions using industry best practices Collaborates with internal and external stakeholders to define, validate, and inte

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s HBM Team in Hyderabad, India. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities Responsible for Design and development of critical Design and Co-optimization objectives, mixed-signal, custom digital block and full chip level integration support. Build and tapeout PWF Reticles Design Engage with Scribe Design team to capture Advanced Packaging requirements and Review TSV design engagement with HIG-HBM DTPCO teams (electrical , thermal and mechanical performance) Creation and Maintenance of DFMEA related to advanced packaging process steps like PWF, die stacking etc Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification

At Affirm, we exist for the moments that matter—giving people a clear, predictable way to pay over time, with no hidden fees, no surprises, and no tradeoffs on what matters most. About the Engineering team The Engineering team builds systems that power Affirm’s mission. We take pride in our craft, building reliable, performant, and scalable solutions that touch every part of the business. Whether we’re enabling new ways to pay, ensuring our platforms can scale to the most demanding levels in the industry, or developing seamless servicing experiences, our focus is on solving complex problems through exceptional engineering. About the role Affirm’s Identity team is mission-critical to the customer checkout experience. When a customer chooses Affirm, one of the first steps is an identity check, and our ability to make the right decision directly impacts conversion, revenue, fraud exposure, and regulatory compliance. Our team owns Identity for all markets outside North America, playing a key role in Affirm’s international expansion. We are responsible for KYC, user lifecycle management, and identity decisioning across multiple regulatory environments. As an Engineering Manager on our team, you’ll help shape how Affirm adapts its core Identity platform to new market dynamics, customer expectations, and compliance requirements. What you’ll do You will lead and grow a well-balanced team of engineers – setting clear expectations, giving direct feedback, and developing each engineer toward their next level. You will own the team’s technical strategy and multi-quarter roadmap, tying it to major experience initiatives that build customer trust and move Affirm’s business, including large-scale redesigns and structural improvements to the identity verification journey. You will empower your tech lead and engineers to hold the design and quality bar, supporting them hands-on throughout technical design and cross-functional alignment. You will own the availability, reliability, an

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. In this role you will: Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. You might thrive in this role if you have: BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Staff Verification Architect and shape modular, scalable verification solutions for next-generation HBM DRAM products across multiple customer platforms! You will be part of a highly multi-functional team of technical domain experts. You will collaborate closely with Design Engineering, Product Engineering, Business Units, and external customer teams to ensure our future HBM roadmap is successful. You will apply your thorough understanding of testbench architecture, custom and SoC verification methodologies, and 2.5D & 3D package integration to analyze bottlenecks and propose innovative solutions targeting scalability, quality, and verification cycle time. Responsibilities: Deliver high-quality, on-time verification plans and architecture collateral across IP-level and SoC-level verification, and develop turnkey solutions for future designs based on look-ahead information from customers and the architecture team Drive co-verification through direct customer interactions, and mentor early-career engineers to strengthen team capability and tech

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure. A hands-on problem solver who excels at debugging and driving signoff through complex verification flows. A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces. A mentor and technical leader passionate about building efficient, manufacturable silicon. What We Need BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verif

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Senior Verification Engineer and contribute to modular, scalable verification solutions for next-generation HBM DRAM products! You will work independently within a multi-functional team of technical domain experts, spanning both IP-level and SoC-level verification. You will collaborate with Design Engineering, Product Engineering, and Business Units to complete the HBM verification roadmap. You will apply your solid understanding of testbench architecture, custom or SoC verification methodologies, and 2.5D & 3D package integration to evaluate issues, define solutions, and broaden your expertise. Responsibilities: Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disc

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Sr. Staff Design Verification Engineer to lead end-to-end verification efforts for our advanced CPU and AI compute platforms. This role is ideal for seasoned engineers with deep expertise in CPU verification who excel at driving complex test plans to closure, mentoring teams, and leveraging modern AI tools to accelerate innovation. This role is hybrid, based out of Boston, Toronto, Ottawa or Santa Clara. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Proven track record leading end-to-end CPU verification across processor cores, caches, interconnects, interrupts, MMU/IOMMU, and cache coherency protocols, with multi-chip and emulation experience a plus. Expert in creating comprehensive test plans and building simulation testbenches using SV-UVM, C/DPI, and Cocotb. Skilled in managing high-volume regression execution, complex failure triage, and driving test plans and coverage metrics to closure. Experienced leader and mentor dedicated to guiding junior engineers and fostering verification best practices across teams. Proficient in leveraging modern AI tools like Copilot, Cursor, Claude, Gemini, and ChatGPT to optimize ver