Design Verification Engineer Intern Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environmen

Job Details: Job Description: The Role and Impact You will be part of a highly skilled, agile design/verification team developing cutting-edge hardware for the NIC, IPU and AI domains. As a senior IP Design Verification Engineer, you will play a crucial role in ensuring the functionality and reliability of complex designs. You will technically lead teams in developing verification plans, creating test benches, and building environments to thoroughly validate meaningful parts of the chip — complex IPs and subsystems. Your work will directly contribute to identifying and resolving bugs in the pre-silicon environment using simulation and/or Formal Property Verification techniques, ensuring robust designs that meet high-performance standards. We are intentional, fast adopters of AI as a working tool. We bring modern AI assistants and automation into every part of the verification flow — planning, stimulus and checker development, coverage analysis, debug and more. Business group You will be joining Intel's Central Engineering Group (CEG), a global organization responsible for designing and verifying industry-leading IPs and architectures that power Intel's NIC, IPU and ASIC products. The group produces innovative technologies and solutions for hyperscalers, cloud providers, networking, AI and other specialized workloads. </spa

Job Details: Job Description: The Role and Impact You will be part of a highly skilled, agile design/verification team developing cutting-edge hardware for the NIC, IPU and AI domains. As an IP Design Verification Engineer, you will play a crucial role in ensuring the functionality and reliability of complex designs. You will develop verification plans, create test benches, and build environments to thoroughly validate meaningful parts of the chip — complex IPs and subsystems. Your work will directly contribute to identifying and resolving bugs in the pre-silicon environment using simulation and/or Formal Property Verification techniques, ensuring robust designs that meet high-performance standards. We are intentional, fast adopters of AI as a working tool. We bring modern AI assistants and automation into every part of the verification flow — planning, stimulus and checker development, coverage analysis, debug and more. Business group You will be joining Intel's Central Engineering Group (CEG), a global organization responsible for designing and verifying industry-leading IPs and architectures that power Intel's NIC, IPU and ASIC products. The group produces innovative technologies and solutions for hyperscalers , cloud providers, networking, AI and other specialized workloads. <d

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics. This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners. In this role, you will: Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic. Design mechanisms for routing, arbitration, ordering, flow con

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks Responsibilities include, but are not limited to: Lead and manage a Design Verification team , ensuring delivery of verification achievements and project commitments Define and drive verification strategy, architecture, and coverage goals for complex designs and programs Own verification planning, execution, reviews, and sign‑off , including functional, timing, and mixed‑signal verification Collaborate with Design Engineering to understand specifications, circuit intent, and performance metrics for design. Partner with multi-functional teams (Product Engineering, Technology Development, CAD, Validation) to ensure alignment and issue resolution Track verification progress, risks, and resource needs; communicate status clearly to partners and leadership Support and guide debugging of complex functional and timing issues identified during pre‑silicon verification Drive continuous improvement of verification methodologies, tools, flows, and best‑known methods (BKMs) Mentor and develop verification engineers through coaching, technical guidance, and performance management Foster a collaborative, inclusive, and high‑performance team culture Promote effective and compliant use of Micron‑approved AI tools to augment verification activities, improve execution efficiency, and support continuous improvement. Education & Experience Necessary for Success <

What We’re Looking For: We’re looking for verification engineers to contribute to and own blocks, sub-systems and potentially the entire wafer-level and cluster-level verification. Ideal Background: Ideal candidates will have: Experience owning verification of blocks and/or sub-systems in SoCs Experience driving verification for complex processor or high performance ASIC designs Experience with performance verification Nice to Have: Experience owning verification of an entire chip or SoC Experience owning verification of a multi-die/multi-chiplet/MCM design Experience in verification of networks, especially multi-network interfaces

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Physical Verification Engineer, you will be a key technical contributor within the Heterogeneous Integration Group (HIG), responsible for defining, executing, and driving sign-off quality physical verification flows for next‑generation HBM logic die and memory‑centric SoCs. You will work across physical design, design rule development, EDA tool teams, foundry interfaces, and product engineering teams to deliver industry‑leading, tape-out-ready silicon under aggressive schedule, quality, and reliability constraints. This role combines full-chip physical verification ownership — including DRC, LVS, ERC, and DFM — with deep collaboration across implementation and silicon bring‑up, ensuring design integrity from layout through first silicon. Responsibilities will include, but are not limited to: Implement physical verification sign‑off for full‑chip and hierarchical designs, including Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), Physical Electrical Rule Check (PERC), antenna checking, and Design for Manufacturability (DFM). Implement and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Memory Systems Engineering team develops the digital and mixed-signal foundation that enables Micron's High Bandwidth Memory (HBM) products. The team works across architecture, PHY, design verification, DFT, and silicon validation functions to deliver innovative memory solutions that achieve demanding performance, power, and reliability targets. In this role, y ou'll receive mentorship from expert engineers while building expertise in sophisticated memory technologies. You will also contribute to the definition, implementation, integration, and validation of HBM base-die digital subsystems. You will collaborate with cross-disciplinary engineering groups to develop robust RTL solutions, support verification activities, and help ensure successful first-pass silicon execution. This position provides an opportunity to gain broad exposure to memory system design, silicon development methodologies, and AI-enabled engineering workflows. Responsibilities Define and implement digital micro-architecture for HBM base-die subsystems, including channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance monitoring, and reliability features. Translate system requirements into timing, power, and area objectives while partnering with physical layer and system architects; develop and maintain interface specifications for bus protocols, clock-domain crossings, and reset architectures. Develop, integra

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: As a Design Engineer for Non-Volatile Memory Datapath Functional Group at Micron, you will support design and validation activities of Datapath and DDR high-speed interfaces of Flash Memory (non-volatile memory) products. Prior experience in Plane Datapath Design is a plus. In this highly challenging role, you will be engaged in high-speed circuits block level and sub-system level design and timing optimization and supervising their layout. You will be working with project/cross-functional teams to understand full chip floor plan and how to fit and place your circuits at full chip level. You will be also working with Application Engineering team to understand the new specs and translate them into circuit requirements. You will also work with CMOS/modeling team to define CMOS characteristics to realize and enable high-speed circuits. In addition to design activities, you will be heavily engaged in high-speed circuits functional and timing validation from base cells all the way to full-chip level using wide variety of simulation tools such as HSPICE, Fast SPICE and NC Verilog. Having 'Design/Verification &#43; AI' approach accelerates the design process. So, you should be able to adept to ‘Design &#43; AI’ approach with N

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Micron’s Memory Systems Engineering team and contribute to the development of premier digital and mixed-signal foundations for our high-bandwidth memory (HBM) products. This position offers an outstanding chance to work intimately with multiple engineering areas, guaranteeing the smooth integration and implementation of HBM base die. Join a motivated team committed to delivering robust first-pass silicon that meets our strict bandwidth, latency, power, and reliability objectives! Responsibilities Assist in defining and carrying out digital micro-architecture for HBM base-die subsystems, covering channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance counters, and reliability features. Translate system requirements into timing, power, and area considerations by partnering with physical layer and system architects, and help maintain interface specifications for bus protocols, clock-domain crossings, and reset strategies. Implement and integrate synthesizable SystemVerilog RTL, including multi-channel logic, interrupts, events, register maps, scan hooks, and design-for-test interfaces, while supporting clean integration and ECO flows. Collaborate with design verification teams to support verification planning, coverage goals, CDC/RDC checks, and debugging of RTL, testbench, and gate-level issues. Support silicon bring-up and post-silicon validation through debug enablement, issue correlation to RTL or architecture, and col

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that deliver the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing some of the world’s most transformative technologies. Our new AI Engineering Campus in Austin will play a central role in building the future of AI computing. The Opportunity As a Mechanical Engineering Intern, you will contribute to the mechanical design and thermal validation of advanced AI hardware. Working alongside experienced mechanical and thermal engineers, you will gain hands-on experience with 3D computer-aided design (CAD), laboratory setup, test development, prototype evaluation, and engineering documentation. Type: 12-week summer internship Timing: May - August (exact dates to be confirmed) Commitment: Full-time What You’ll Do Contribute to mechanical design activities using Creo or comparable 3D CAD software, including part modeling, assemblies, drawings, and design updates under the guidance of experienced engineers. Work with the thermal engineering team to develop test procedures and help set up laboratory capabilities for evaluating AI hardware. Support thermal and mechanical testing using appropriate laboratory equipment; collect, organize, and analyze test data. Assist the mechanical and thermal design teams with prototype evaluation, troubleshooting, design verification, and documentation of findings. Collaborate with cross-functional engineering partners, communicate progress and issues clearly, and follow applicable laboratory and safety procedures. What You’ll Bring Current enrollment in a bachelor's, master's, or doctoral program in mechanical engineering or a related discipline during the internship. Students in other disciplines with relevant mechanical engineering exper

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Position Description: As a technical member of Micron’s ASIC Verification team, you will have a key role in development of advanced verification components for complex IP designs, while ensuring on time delivery with best-in-class quality. Typical tasks include: development of new simulation environments, execution of verification plans while interfacing with design teams, and debugging complex problems. You must be familiar with constrained random verification and functional coverage closure. Additionally, you will be a self-starter, possess excellent analytical and problem solving/debugging skills, and have excellent verbal and written communication skills. Responsibilities include, but not limited to: ASIC/FPGA design verification experience with UVM methodologies Developing UVM-based SystemVerilog test-benches. Defining block, sub-system level verification plans. Understanding and knowledge of verification methodologies, flows and quality metrics. Excellent problem-solving skills. This role is expected to utilize Micron-approved AI tools and AI-enabled workflows to improve engineering productivity Team player with great interpersonal communication skills. Minimum Qualifications: Strong leadership and communication skills, with the ability to convey complex technical concepts to other peers in verbal and written form Experience with python programming language A proven ability to achieve result

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The ASIC Validation team plays a critical role in bringing Micron's next-generation silicon products to life by validating and characterizing new devices as they return from fabrication. Working closely with design, verification, and firmware teams, the group develops innovative validation methodologies, automation solutions, and AI-enabled workflows to ensure product quality, performance, and reliability. As an ASIC Validation Intern, you will work alongside experienced engineers to validate newly developed silicon and enhance the validation infrastructure used across engineering teams. This role provides hands-on experience with hardware validation, lab equipment, automation, data analysis, and AI-assisted engineering workflows while contributing directly to the successful bring-up of next-generation ASIC products. Responsibilities Collaborate with validation, design verification, and firmware teams to support silicon bring-up, testing, and validation activities for new ASIC devices. Use laboratory equipment, automation tools, and validation environments to characterize device functionality and performance. Develop or enhance scripts, automation solutions, and AI-assisted workflows to improve validation efficiency, failure analysis, and reporting. Analyze validation results, debug complex issues, and evaluate AI-generated insights while applying sound engineering judgment. Document technical findings, communicate project results, and present recommendations to engineering teams. </

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s DRAM Design Engineering Group (DDEG) is where bold ideas become real technology. We push the limits of memory and storage innovation, and we thrive in a collaborative environment where engineers learn, build, and solve challenges together. We are driven by curiosity, creativity, and the pursuit of better solutions every day! We are seeking a Principal or Member of Technical Staff (MTS) in Analog Design to join our DRAM IP Design team. As a Principal/ MTS, you will help shape the next generation of Micron's memory products, while working closely with global design, verification, and product teams to bring innovative circuit designs from concept to silicon. Your work will directly influence product performance, quality, and reliability—and contribute to advancements that define the semiconductor industry. Responsibilities: Design, optimize, and verify block‑level analog and mixed-signal circuits for DRAM projects. Work with the internal data science team and EDA vendors to leverage and improve AI-assisted design flow and circuits optimization. Propose, evaluate and implement new or improved circuit topology to further enhance PPAC of the circuit block. Improve design verification scope and coverage to increase circuit robustness to enhance mass production yield. Partner with global design groups and provide layout guidance through post‑layout simulation. Compare silicon

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s DRAM Design Engineering Group (DDEG) is where bold ideas become real technology. We push the limits of memory and storage innovation, and we thrive in a collaborative environment where engineers learn, build, and solve challenges together. We are driven by curiosity, creativity, and the pursuit of better solutions every day! We are seeking a Principal or Member of Technical Staff (MTS) in Analog Design to join our DRAM IP Design team. As a Principal/ MTS, you will help shape the next generation of Micron's memory products, while working closely with global design, verification, and product teams to bring innovative circuit designs from concept to silicon. Your work will directly influence product performance, quality, and reliability—and contribute to advancements that define the semiconductor industry. Responsibilities: Design, optimize, and verify block‑level analog and mixed-signal circuits for DRAM projects. Work with the internal data science team and EDA vendors to leverage Agentic- AI and improve AI-assisted design flow and circuits optimization. Propose, evaluate and implement new or improved circuit topology to further enhance PPAC of the circuit block. Improve design verification scope and coverage to increase circuit robustness to enhance mass production yield. Partner with global design groups and provide layout guidance through post‑layout simulation. Com