Dft Lead Jobs

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products. You will have the chance to define, prototype and deploy next generation DFX architectures and methodologies across all our products. This includes high speed test access architectures, the in-system-test architecture, ISO26262 functional safety diagnostic for in-field testing and beyond, silicon debug & bring-up, productization, and silicon life-cycle management among others As a member on our DFX Architecture team, your responsibility will be to craft key DFX architecture and methodologies to meet system level safety diagnostic test quality, in-field test quality, advanced defect screening and diagnosis to enable SLM for automotive, industrial, and robotics safety platforms etc. Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI,

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas. This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs. Partner with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips. You will work on post-silicon data analysis for power to architect the next-gen solutions. In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions. Help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equivalent experience) with 12+, MSEE with 10+, or PhD with 6+ years of experience in DFT design & power

Senior DFT - Silicon Validation Engineer — CA, Santa Clara. Apply via Workday.

Senior DFT Engineer — US, CA, Santa Clara. Apply via Workday.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas. This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs. You will work with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips. You will work on post-silicon data analysis for power to architect the next-gen solutions. In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions. You will also help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equ

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work with pre-silicon and post-silicon data analytics - visualization, insights and modeling. Design and uphold sturdy data pipelines and ETL processes for the ingestion and processing of DFX Engineering data from various origins Lead engineering efforts by collaborating with cross-functional teams (execution, analytics, data science, product) to define data requirements and ensure data quality and consistency You will work on hard-to-solve problems in the Design For Test space which will involve application of algorithm design, using statistical tools to analyze and interpret complex datasets and explorations using Applied AI methods. In addition, you will help develop and deploy DFT methodologies for our next generation products using Gen AI solutions. You will also help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equivalent experience) with 5+, MSEE with 3+, or PhD wi

Principal DFT Engineer, HBM — 2 Locations. Apply via Workday.

Job Details: Job Description: The Role and Impact Are you ready to make a significant contribution to cutting-edge semiconductor designs? As a DFT Design Engineer, you will play a critical role in shaping the testability, debuggability and reliability of complex SoC (System-on-Chip) designs. You will work closely with cross-functional teams, influencing designs from concept to production, and ensuring our products meet the highest quality standards. In this role, you will develop innovative DFT/DFD methodologies, optimize workflow with AI, and enhance post silicon efficiency. Your work will directly impact Intel's ability to deliver world-class semiconductor solutions that advance technology across industries. Key Responsibilities : Develop and implement advanced DFT methodologies for complex SoC designs to maximize test coverage and efficiency. Collaborate with design, verification, and manufacturing teams to define and optimize post silicon strategies and requirements. Integrate DFT/DFD features into RTL and ensure verification of design for testability requirements. Collaborate with post-silicon teams to debug and validate DFT features. Stay current with emerging trends, AI adoption and technologies in DFT/DFD to ensure best practices are incorporated into workflows. Qualifications: Minimum Qualifications : Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of experience in DFT, SoC design, or related semiconductor design areas. Expertise in RTL design using hardware description languages like Verilog, VHDL, or SystemVerilog. Preferred Qualifications : Familiar with AI application. Familiarity w

Staff/Principal Engineer - HBM Design for Test (DFT) — Richardson, TX. Apply via Workday.

Principal Engineer – HBM Design for Test (DFT) — Richardson, TX. Apply via Workday.

SR ENGINEER, DDEG DESMETH DFT — Hyderabad - Phoenix Aquila, India. Apply via Workday.

SR Engineer, ASIC DFT — Hyderabad - Phoenix Aquila, India. Apply via Workday.

New College Grad - Design Engineer, HBM DFT — Richardson, TX. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Location Singapore Department NAND Probe Product Engineering Project Title AI-Enabled Test Mode Innovation and Integration Project Description The NAND Probe Product Engineering Intern will undertake a structured learning and innovation project focused on test mode development concepts, silicon validation methodologies, and AI-Enabled engineering solutions for advanced NAND technologies. Working alongside experienced Product and Design Engineers, the intern will develop knowledge of NAND test methodologies, Design for Test (DFT) concepts, and silicon validation processes. This internship combines semiconductor engineering fundamentals with Artificial Intelligence, data analytics, automation, and Generative AI technologies, providing an opportunity to explore how AI-Enabled tools and Agentic AI solutions can enhance engineering learning, technical knowledge discovery, test effectiveness, and innovation. Objective of the Project The intern will have the opportunity to: Develop an understanding of NAND architecture, probe testing concepts, Design for Test methodologies, and test mode integration practices. Explore engineering datasets to identify product behaviour

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. The Package Health Analyst will contribute to the development and execution of package health monitoring, simulation, and characterization activities. This role involves hands-on engineering work in DFT, data analysis, and reliability testing to ensure robust packaging solutions Key Responsibilities Package Health Metrics & Monitoring Define quantitative package health metrics Develop detection mechanisms and monitoring dashboards for continuous health assessment. Perform electrical and mechanical characterization of packages. Inline Defect Characterization Implement real-time defect detection and classification (critical vs. non-critical). Conduct next-level characterization for critical defects and integrate findings into predictive models. Advanced Analytics & Knowledge Base Perform correlation and causation studies between process variables, defect patterns, and reliability outcomes. Build and maintain a structured knowledge base for package health learnings to enable NPI handover and future technodes. End-to-End Traceability </