Hardware Systems Architect Jobs

As a Software Engineer on the Firmware team, you will own the software integration, performance, optimization, and debugging of our TCU (Telematics Control Unit). Managing a complex architecture that integrates third-party hardware with our autonomous vehicle platform, you will analyze diagnostics and log outputs across cellular networks, 4G/5G modems, internal software layers, Wi-Fi, and Bluetooth. You will not only reactively troubleshoot complex field issues but also proactively architect and develop robust host-side connectivity software to handle cellular edge cases and vulnerabilities before they impact operations. Your work will directly safeguard the safety, reliability, and scaling of the Zoox autonomous fleet. Robust, low-latency connectivity is fundamental to autonomous vehicle deployment, powering essential real-time cloud services, fleet management pipelines, and teleoperation capabilities. By ensuring our vehicles maintain seamless, high-performance connections under the most demanding real-world conditions, you will bridge the gap between cutting-edge hardware, cloud infrastructure, and test systems to enable Zoox to deliver the future of autonomous mobility. You will leverage a profound understanding of how these stacks operate to define the architecture, utilize vendor interfaces, and debug complex cross-layer issues. Responsibilities Contribute and Develop: Contribute to Zoox's firmware and cellular wireless connectivity stack (LTE/5G), developing and enhancing connectivity features across multiple generations of hardware. Vendor Integration: Act as the primary technical expert working with cellular chipset vendors (e.g., Qualcomm) to integrate their proprietary firmware, SW stacks, and L1-L3 implementations into our custom embedded Linux platform. Architecture Definition: Define, architect, and validate the critical software interfaces betw

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will build the low-level device runtime that turns compiled programs into efficient, functional and performant execution on OpenAI’s custom AI accelerator. This software will schedule kernel launches, manage device memory and address spaces, coordinate synchronization, and expose reliable abstractions to higher-level runtimes and frameworks. You will work at the boundary of software and hardware, partnering with compiler, kernel, architecture, verification, and silicon teams to define interfaces and validate behavior. You will also use and improve event-based, cycle-accurate simulation to develop runtime capabilities before silicon is available, diagnose performance and correctness issues, and guide hardware-software co-design. In this role, you will: Design and implement the low-level device runtime for OpenAI custom silicon. Build kernel-launch scheduling, command submission, queueing, dependency tracking, and completion handling. Manage device memory spaces, allocation, virtual-to-physical mappings, data movement, and lifetime across concurrent workloads. Implement synchronization primitives, events, barriers, streams, and ordering guarantees that are correct and efficient. Define clean interfaces between the runtime, drivers, firmware, compiler-generated code, kernels, and higher-level execution systems. Use event-based, cycle-accurate simulators to develop, validate, debug, and performance-tune runtime behavior before and after silicon availability. Di

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will build the model runtime within the inference engine that executes complex, frontier models at scale on OpenAI’s custom silicon. The runtime will sit between models running on the hardware and the upper layers of the cluster serving software stack, translating demanding inference workloads into efficient execution while optimizing for throughput, latency, utilization, and reliability. You will work across model architecture, distributed systems, compilers, kernels, and silicon to design a production-grade runtime comparable in ambition to systems such as vLLM and SGLang, but customized and optimized for OpenAI’s AI accelerator. Your work will shape how new model capabilities map onto the platform and how quickly custom silicon can deliver meaningful performance in production. In this role, you will: Design and implement the LLM inference runtime for frontier models running on custom silicon. Build scheduling, continuous batching, memory management, KV-cache management, and execution orchestration for high-performance inference. Develop distributed execution strategies across chips, hosts, and racks, including model partitioning, communication, and synchronization. Optimize end-to-end latency, throughput, memory efficiency, and hardware utilization across diverse model architectures and serving workloads. Partner with kernel, compiler, architecture, and silicon teams to co-design interfaces and remove performance bottlenecks across the stack. Enable new

EnCharge AI is building a new generation of AI compute systems designed to deliver dramatically higher energy efficiency for AI inference. Our technology combines innovative compute architectures with a full-stack software platform spanning silicon, firmware, drivers, compilers, runtimes, and AI model enablement. We are looking for a Technical Program Manager - Embedded Software to drive execution across our embedded software organization and ensure tight alignment between firmware, drivers, hardware, architecture, compiler, runtime, and system teams. About the Role As Embedded SW TPM, you will be the connective tissue between silicon, platforms and systems teams, driving the embedded and low-level software programs that enable EN100 (and future accelerators) to run real AI workloads reliably and efficiently. You'll own the program plan from architecture through bring-up, pre-/post- silicon validation, and customer/OEM deployment to surface risks before they become blockers and keeping a hardware-coupled software org moving in lockstep with silicon milestones. What You'll Do • Own end-to-end program management for embedded software workstreams: device drivers, firmware, boot-loaders and board support packages for EnCharge accelerators. • Build and maintain integrated program schedules that align embedded software milestones with chip tape-out, silicon bring-up, board bring-up, and customer/OEM delivery dates. • Partner closely with embedded software, ASIC/hardware, platform and validation teams to define scope, sequence dependencies, and track execution against plan. • Identify, track, and drive resolution of cross-team risks and blockers (e.g., silicon errata affecting driver behavior, toolchain dependencies, host OS/driver compatibility). • Drive silicon bring-up and platform enablement, including early firmware, boot flows, device initialization, memory management, command submission, interrupts, power management, and hardware/software integration. • Run the prog

About the Role Systems Technology, Inc. (STI) is seeking an Embedded Software Engineer - UAS to join our Aerospace division, supporting flight software development for next-generation UAS and counter-UAS platforms. You'll work at the intersection of guidance, navigation, and control (GNC) software and the embedded hardware it runs on — writing, testing, and debugging flight-critical code for fault-tolerant flight controllers and mission systems. This is hands-on work: you'll be as comfortable on an oscilloscope bench as you are in a debugger. What You'll Do Design, implement, and test embedded C/C++ software for flight control and mission computer systems Develop and debug low-level drivers and communication interfaces (CAN, SPI, I2C, UART, PWM) between flight controllers, sensors, and actuators Support bring-up, integration, and troubleshooting of embedded hardware alongside electrical and mechanical engineers Contribute to software architecture for fault-tolerant, dual-core flight control systems Participate in flight testing, telemetry analysis, and post-flight debugging Collaborate with GNC engineers to translate control algorithms into deployable flight code Maintain code quality through version control, code review, and structured testing practices Minimum Qualifications 3–5 years of professional software development experience Proficiency in C and/or C++ Strong problem-solving, analysis, and debugging skills U.S. Person status required, as defined by ITAR (22 CFR 120.15), due to the export-controlled nature of this work This is an on-site position based in Hawthorne / Los Angeles, CA; remote or hybrid work is not available Preferred Qualifications Experience with UAS, UAVs, drones, or RC aircraft Experience developing software for embedded systems or microcontrollers Familiarity with embedded communication protocols such as CAN, SPI, I2C, UART, or PWM Familiarity with Git and modern software development practices Familiarity with debugging tools such as logic

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role We're looking for an Optical Interconnect System Engineer to design, qualify, and deploy scalable optical connectivity for large-scale AI infrastructure. This role spans fiber-system architecture, optical-mechanical integration, validation, reliability, deployment, and serviceability. You will work with optical, mechanical, electrical, networking, manufacturing, reliability, and data-center teams to translate system needs into practical interconnect solutions. This is a hands-on role for someone who can connect design decisions with installation, qualification, troubleshooting, and long-term operational performance. In this role, you will: Define optical interconnect architectures and requirements across hardware platforms and rack-level systems. Design high-density fiber systems for performance, density, reliability, installation, and serviceability. Lead optical-mechanical integration and cross-functional design reviews. Develop test and qualification plans for optical components, modules, switching platforms, and integrated systems. Own optical loss budgets, routing guidelines, handling requirements, and serviceability criteria. Support system bring-up, deployment, troubleshooting, failure analysis, and reliability improvement. Create reusable design guidelines, interface requirements, and qualification methods. You might thrive in this role if you have: Core experience Experience desi

About the Team The GPT Infrastructure team builds systems that turn advances in model inference and optimization into reliable production capabilities. We enable OpenAI workloads to be qualified and optimized across new accelerator platforms without requiring a one-off port and tuning effort for every hardware target. Our work spans distributed systems, model execution, compilers and runtimes, performance engineering, secure partner integrations, evaluation systems, and developer tooling. We build the infrastructure that makes optimization workflows automated, reproducible, and trustworthy. About the Role We are seeking a software engineer to help build the platform that qualifies and optimizes inference workloads across heterogeneous compute environments. You will develop both OpenAI-hosted services and secure partner-side software for running long-lived optimization workflows. These workflows generate candidate kernels, runtime configurations, and serving-stack changes; compile and execute them on target hardware; verify their correctness; measure their performance; and use the results to guide further optimization. You will work across model architecture, distributed execution, compilers, runtimes, networking, and accelerator systems. A central part of the role is turning research prototypes and one-off hardware bring-up efforts into reliable, reusable infrastructure with clear contracts, reproducible results, strong observability, and well-defined security boundaries. Key Responsibilities Design, build, and operate APIs and control-plane services for long-running workload qualification and optimization campaigns, including scheduling, retries, checkpointing, resource budgets, and observability. Build secure partner-side execution and evaluation software that can compile, run, verify, profile, and benchmark candidate artifacts on accelerator hardware. Integrate model workloads, hardware profiles, compiler toolchains, runtimes, serving engines, and distributed-exe

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 8-12 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root cau

Perplexity is looking for a highly skilled Senior or Expert Systems Engineer to join our Search Core team. This role is critical to building next-generation search products and technologies. You will help drive key decisions around the architecture, design, and implementation of foundational components in our technical stack. Responsibilities Design and build core search engine components, including indexing pipelines, retrieval algorithms, and ranking systems that operate at the scale of billions of pages Develop streaming and batch data processing systems for search index construction in a high-load environment Push the limits of hardware performance through low-level optimizations and systems-level tuning Tackle challenges in multithreading, concurrency, and system-level optimization Qualifications 3+ years of hands-on experience in systems programming (Rust, C++, C, or similar) Ownership of full project lifecycle — you don't just write a fast inner loop, you care about how the system is built, deployed, operated, and scaled in production Knowledge of Python or other scripting languages Passion for writing clean, efficient, and scalable systems-level code Strong knowledge of algorithms and data structures, and the ability to apply them effectively Deep understanding of multithreading, including various approaches, challenges, and trade-offs Experience building high-load, distributed, and hardware-adjacent services Solid understanding of Linux internals (syscalls, networking stack, memory model, kernel tuning) Familiarity with low-level optimization techniques (memory management, cache efficiency, SIMD, profiling) Preferred Qualifications Experience developing core components of search engines, databases, or information retrieval systems Understanding of search fundamentals: indexing, query parsing, ranking, and relevance Experience with trading systems or other latency-sensitive real-time systems Familiarity with cloud services, Kubernetes, and AWS infrastructure

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will define and build the CI/CD systems that qualify frontier models and the software stack running on OpenAI’s custom AI accelerators. Your work will make correctness, performance, and stability measurable on every change, from individual commits through production releases. This role spans model workloads, accelerator software, systems infrastructure, and developer productivity. You will establish scalable CI/CD, GitOps, and monorepo practices; design trustworthy regression and benchmarking pipelines; and partner with model, compiler, kernel, runtime, firmware, and hardware teams to shorten feedback loops without compromising production readiness. In this role, you will: Define the model CI strategy for frontier models running on OpenAI custom silicon and integrated accelerator systems. Build production CI/CD pipelines for functional regression, performance benchmarking, software stability, and release qualification. Design representative test matrices across models, configurations, hardware generations, software components, and deployment environments. Create reliable performance baselines, regression detection, bisect and triage workflows, and clear ownership for failures. Establish GitOps practices for reproducible configuration, promotion, rollback, auditability, and environment consistency. Shape monorepo architecture, dependency management, build and test boundaries, change validation, and developer workflows at scale. Develop scalable orchestration

About Mach Industries Founded in 2023, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms. At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 350 employees, we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role We are seeking a engineer to join our new and non-defense consumer robotics program. Robotic hands are a dedicated area of development for our group and this role offers significant ownership in solving challenges related to handling everyday objects with different shapes, weights, and textures. Our robotics engineers work end to end to build complete systems, partnering closely with mechanical, electrical, and software engineers to turn concepts into products. Key Responsibilities Make early architecture and component decisions with safety, manufacturability, reliability, and serviceability in mind Own decisions about mechanisms that determine dexterity, strength, and range of motion Develop and tune hand controls so the robot can grasp securely, adjust its grip, and handle fragile or unfamiliar objects Champion systems integration by partnering with electrical, mechanical, and software peers to bring the complete hand system to life Conduct rigorous reliability testing, failure analysis, and root-cause investigations, using experiments and analysis to guide the next design Required Qualifications Experience designing robotic hand mechanisms and actuator control systems Demonstrated hands-on experience turning ideas into hardware an

About the Team DoorDash Labs, established in 2018, serves as the innovation hub for DoorDash, focusing on developing automation and robotics solutions to enhance last-mile logistics. The team's mission is to create technologies that support and augment human networks, aiming to improve efficiency for Dashers, merchants, and consumers alike. We’re ruthlessly focused on business impact. We are a highly senior team composed of former pioneers from a variety of different robotics industries. As of 2025, DoorDash has completed 10B lifetime deliveries. We’re focused on how to do the next 10B even better. About the Role We’re looking for a Senior/Staff electrical and firmware engineer who designs the board and writes the firmware for connected consumer and enterprise devices, including tablets, POS systems, peripherals, and emerging robotics applications. In this role, you will take connected devices from ambiguous user or business needs through system architecture, rapid prototyping, board design, firmware implementation, bring-up, field deployment, and production transition. The ideal candidate has a passion for building and shipping reliable hardware at scale and thrives in an environment that demands technical depth and high-quality execution across multiple concurrent programs. This is a build-heavy role on a small, senior team. You’re excited about this opportunity because you will… Own connected devices end to end, including: Own connected devices from an ambiguous product need through field deployment. Work across the hardware and firmware boundary instead of handing work between specialists. Explore uncertain product ideas through rapid prototypes and experiments. Make consequential tradeoffs on a small, senior team with direct exposure to users and field behavior. Key Responsibilities Translate user and business needs into an integrated electrical and firmware architecture. Design compute-based, mixed-signal boards incorporating processors

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is hiring a System-Level Test (SLT) Engineer to ensure our silicon behaves predictably when running real workloads in real systems. You’ll build the software and system infrastructure that enables validation tests to operate reliably in manufacturing, while applying structured debug to separate hardware issues from software, interface, and environmental effects. This role is ideal for someone who understands how tests are constructed and how silicon responds under stress—and who can turn that insight into scalable, production-ready solutions. Candidates will be assessed for the appropriate level during the interview process, and the offer level may differ from the level listed in this posting. This role is hybrid, based out of Austin,TX; Santa Clara,CA; or Fort Collins, CO . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 10+ years of experience in system-level test, embedded systems, software architecture, or hardware/software integration, with strong skills in C/C++, Python, or similar languages. You apply object-oriented design principles to build modular, maintainable, and extensible test frameworks

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that deliver the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing some of the world’s most transformative technologies. Our new AI Engineering Campus in Austin will play a central role in building the future of AI computing. The Opportunity As a Graduate Performance Engineer, you will contribute to the design, integration, bring-up, and validation of complex server- and rack-level performance of elaborate, large-scale systems. You will work alongside experienced engineers, software developer, and cross-functional partners while building practical skills in component, system and scale up/out performance optimization and design. Start: September, 2027 Location: Austin, Texas, USA What You’ll Do Support the design, peer review, bring-up, and debug of complex server- and rack-level systems. Assist with modeling, design and evaluation of the complete software and hardware stack identifying performance bottlenecks, possible solutions and testing those outcomes. Collaborate with many different teams across both hardware and software development and testing. What You’ll Bring A bachelor’s or master’s degree in electrical engineering, computer engineering, or a related discipline, completed before the role’s start date. Equivalent relevant education or practical experience will also be considered. Foundational knowledge of software development, hardware architecture and general understanding of performance implications. Hands-on experience gained through coursework, laboratories, internships, research, student projects, or personal projects. Ability to analyze technical problems, document your work, communicate clearly, and collaborate effectively. Curiosity, sound engineering judgment, a