High Speed Hardware Developer Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP). You’ll collaborate closely with Tenstorrent experts and leaders across the USA, Japan, and other global sites, as well as external partners, to deliver world-class CPU and AI silicon. In this role, you will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, contributing directly to performance, power, and area outcomes on advanced process nodes. This role is remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An experienced physical design engineer with at least 10 years of relevant experience, who thrives in complex, multi-stakeholder projects. Detail-driven, with a strong sense of ownership from synthesis through design closure. Comfortable working at advanced nodes (3nm and below) and multi-GHz designs. A collaborative team player who enjoys mentoring others and influencing methodology. Clear communicator who can balance technical depth with schedule and resource constraints. &nbsp

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Job title Senior DFT Engineer Job description We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. Your responsibilities Integrate and verify test features in digital designs for effective manufacturing testing and silicon debug. Key responsibilities include: Building entire chip-level DFT strategies Inserting DFTs, including scan chains, memory BIST, and JTAG Collaborating with RTL, physical design, and verification teams for testability throughout the design flow Scripting and automating DFT flows using industry-standard EDA tools (e.g., Cadence, Synopsys, Siemens) Running and analyzing ATPG and fault coverage reports Supporting silicon bring-up and debug related to test features Knowledge of advanced silicon technologies and methodologies for test coverage optimization Experience with formal verification and signoff of inserted DFT logic Strong communication and collaboration skills for cross-functional teamwork Exp

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products. You will have the chance to define, prototype and deploy next generation DFX architectures and methodologies across all our products. This includes high speed test access architectures, the in-system-test architecture, ISO26262 functional safety diagnostic for in-field testing and beyond, silicon debug & bring-up, productization, and silicon life-cycle management among others As a member on our DFX Architecture team, your responsibility will be to craft key DFX architecture and methodologies to meet system level safety diagnostic test quality, in-field test quality, advanced defect screening and diagnosis to enable SLM for automotive, industrial, and robotics safety platforms etc. Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Craft and analyze digital and analog circuits used in the development of memory products including simulating, optimizing, and floor planning DRAM circuits. Collaborate with various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to proactively craft HBM products that optimize all manufacturing functions and assure the best performance, power, cost, quality, reliability, time-to-market, and customer happiness. Innovate and integrate end-toend groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). Employer will accept a Master’s degree in Electrical Engineering, Physics, Computer Engineering, Semiconductor Engineering or a related field and 10 years of experience in the job offered or in a related field. Position requires: 1. High-speed memory design on data paths, from I/O interface to core array 2. 2. Power domain network analysis 3. Memory test architectures like MBIST and production silicon validation 4. Digital design methodologies experience including RTL design, synthesis, and physical implementation 5. ASIC design development using digital design 6. Memory core timing, latency control, and signal integrity consideration in advanced designs <p style="

Zscaler (NASDAQ: ZS) accelerates digital transformation so customers can be more agile, efficient, resilient, and secure. The Zscaler Zero Trust Exchange platform protects thousands of customers from cyberattacks and data loss by securely connecting users, devices, and applications in any location. Distributed across 200+ public data centers globally and thousands of private sites at the edge, the SASE-based Zero Trust Exchange is the world’s largest in-line cloud security platform. We believe the future of work is Human + AI and are building an AI-native enterprise where human potential is amplified by machine intelligence to solve the world’s hardest security challenges. Driven by deep customer obsession, we are committed to the mission, outcome, and to each other. We bring these commitments to life through three core behaviors: ownership and collaboration, trust through outcomes and impact, and a challenge culture with ongoing feedback. Ready to make an impact at the company pioneering security transformation in the AI era? Join us at Zscaler. Role We are looking for a Staff Software Development Engineer to join our team. This is a hybrid role based in Bangalore, reporting to the Director, of Engineering. What you’ll do (Role Expectations) Lead ZCC feature design and hands-on C++ implementation on Linux environment. Take full technical ownership of complex projects, from concept to deployment. Elevate code quality and enforce best practices to ensure a robust, efficient, and secure client. Ability to process packets at both ingress and egress points at very high speed so that client using the system does not perceive any increased latencies. To work cross-functionally with the Quality Assurance team to test the work product, and influence the testing to make the product ready for deployment Who You Are (Success Profile) You thrive in ambiguity. You're comfortable building the path as you walk it. You thrive in a dynamic environme

We are seeking a detail-oriented PCB Layout Engineer to maintain electronic component libraries and develop printed circuit board layouts. This role works closely with electrical engineering, mechanical engineering, procurement, and NPI to ensure component data and PCB designs are accurate, consistent, and ready for production. This position is in Austin, Texas. Key Responsibilities Create, verify, and maintain schematic symbols, PCB footprints, and associated 3D models. Validate component pin assignments, dimensions, land patterns, and library attributes against manufacturer documentation. Maintain library naming conventions, revision control, and component approval processes. Develop PCB layouts from approved schematics, including component placement, routing, stackup coordination, and design rule setup. Collaborate with engineers to address electrical, mechanical, thermal, and manufacturing requirements. Run design rule checks, resolve layout issues, and participate in design reviews. Prepare fabrication and assembly deliverables, including Gerber or ODB++ files, drill files, drawings, and pick-and-place data. Coordinate with PCB fabricators and assembly suppliers to resolve manufacturing questions. Support engineering changes and maintain accurate release documentation. Work with procurement and engineering to identify obsolete components and evaluate suitable alternatives. Required Qualifications Experience with setting up PCB design and electronic component library management. Proficiency in Cadence Allegro/OrCAD. Ability to interpret schematics, component datasheets, and mechanical drawings. Working knowledge of PCB fabrication, assembly processes, and design for manufacturability. Familiarity with relevant IPC standards for PCB design and component land patterns. Strong attention to detail, documentation skills, and ability to manage competing priorities. Experience with multilayer, high-density, mixed-signal, and high-speed PCB designs. Familiarity w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Principal ASIC Design Engineer About the Role At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute. As the Principal ASIC Design Engineer , you will be the primary digital contributor on a deliberately small, senior team — united around the goal of carrying high-speed interface technologies from architecture to tape-out. The team’s analog and chip-level architecture is anchored by a deeply experienced analog custom design engineer; your role is to be the authoritative digital voice — owning RTL design and micro-architecture of the digital blocks, defining timing constraints, supporting verification, and serving as the key interface between the digital design and the analog and layout specialists who will carry the implementation through to silicon. On a test ASIC of this scope, the front-end digital work is the critical path, with contractor and layout support engaged as bandwidth demands warrant. What You’ll Own Digital Block Architecture & RTL Design Own the micro-architecture and RTL implement

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction. You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it! What you’ll be doing: You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will: Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs. Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution. Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging. Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs. Shape the program’s technical narrative by surfacing key risks, trade

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. Job Summary The Representative I is the initial point of contact for Prior Authorization requests from members, providers, and a diverse customer base. The Rep I will make the determination if a complex request should be transferred to a pharmacist for assistance. Additionally, the Rep I is responsible for maintaining complete, timely, and accurate documentation of all approvals and denials. In order to be successful in this role you will need proficiency pronouncing drug names and diagnosis and recognizing medical terminology. As well as navigating multiple software systems to document conversations and outcomes, which require keyboarding skills. This position requires schedule flexibility including rotations through nights, weekend and holiday coverage. Required Qualifications - 1 year experience in customer service or call center environment - Must be able to work from home - Have high speed internet Preferred Qualifications - Previous experience in pharmacy or healthcare industry. - Associate's or Bachelor's Degree. Pharmacy Technician License Education High School Diploma or equivalent GED Anticipated Weekly Hours 40 <p sty

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. Position Summary The Technician I is the initial point of contact for Prior Authorization requests from members, providers, and a diverse customer base. The Tech I will make the determination if a complex request should be transferred to a pharmacist for assistance. Additionally, the Tech I is responsible for maintaining complete, timely, and accurate documentation of all approvals and denials. In order to be successful in this role you will need proficiency pronouncing drug names and diagnosis and recognizing medical terminology. As well as navigating multiple software systems to document conversations and outcomes, which require keyboarding skills. This position requires schedule flexibility including rotations through nights, weekend and holiday coverage. Required Qualifications - 1 year experience in customer service or call center environment - Must be able to work from home - Have high speed internet Preferred Qualifications - Previous experience in pharmacy or healthcare industry. - Associate's or Bachelor's Degree. Pharmacy Technician License Education High School Diploma or equivalent GED Anticipated Weekly Hours 40<p style="text

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Principal Signal Integrity Engineer — Interface Pathfinding About the Role At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team operates at the leading edge of that mission — serving as a bridge between corporate strategy and engineering through forward-looking investigation and development of energy-efficient bandwidth solutions. Our work spans innovative circuit, signaling, packaging, and interconnect solutions with a 3–5 year technology horizon, grounded in rigorous analysis, hands-on measurement, and a commitment to building a robust intellectual property portfolio. As a Principal Signal Integrity Engineer , you will be a core technical contributor on a deliberately small, senior team united around the goal of preparing high-speed interface innovations for high-confidence product adoption. What You’ll Work On Micron’s Interface Pathfinding team investigates and validates novel interconnect and signaling solutions for high-speed memory and die-to-die interfaces. The signal integrity scope is broad and analytically deep — spanning electrical modeling, channel analysis, and substrate evaluation — with an emphasis on original analysis rather than execution of established playbooks. Key signal integrity domains include: Intercon

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an Electrical Design Engineer in the Systems Integration Group (SIG) of Micron Technology, Inc, you will design load boards that support semiconductor memory manufacturing, as well as resolve issues with and develop improvements to deployed automated test equipment (ATE) products. Load boards, used for testing memory devices after they are manufactured & packaged, are the contact interface between ATE and pins of the device under test (DUT). Load boards contain the necessary components to: setup the DUT for correct testing by the ATE; route power, test, and response signals between the DUT and the ATE; provide additional test capabilities that the ATE may not be able to provide; and, alternately, testing or calibrate the ATE itself. Load board design considerations, like other PCB assemblies, include DC power supply distribution, clock & digital routing, and high-speed signal integrity. You will apply circuit theory to design load board solutions working closely with other team members located around the world that include other engineering disciplines, technicians, procurement, planning, and external contract manufacturers. Responsibilities and Tasks Develop requirements specifications Analog and digital circuit design and simulation Schematic capture Work closely with layout designers to develop PCBs Author test plans and lab repo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Principal Signal Integrity Engineer — Interface Pathfinding About the Role At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team operates at the leading edge of that mission — serving as a bridge between corporate strategy and engineering through forward-looking investigation and development of energy-efficient bandwidth solutions. Our work spans innovative circuit, signaling, packaging, and interconnect solutions with a 3–5 year technology horizon, grounded in rigorous analysis, hands-on measurement, and a commitment to building a robust intellectual property portfolio. As a Principal Signal Integrity Engineer , you will be a core technical contributor on a deliberately small, senior team united around the goal of preparing high-speed interface innovations for high-confidence product adoption. What You’ll Work On Micron’s Interface Pathfinding team investigates and validates novel interconnect and signaling solutions for high-speed memory and die-to-die interfaces. The signal integrity scope is broad and analytically deep — spanning electrical modeling, channel analysis, and substrate evaluation — with an emphasis on original analysis rather than execution of established playbooks. Key signal integrity domains include: Interconnect Modeling — Generating an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Post-Silicon Yield & RMA Leadership Lead end-to-end investigation of silicon yield loss, field returns, customer escalations, and reliability failures. Drive root-cause analysis for complex silicon issues spanning process, design, test, package, and system interactions. Develop hypothesis-driven debug strategies and coordinate multi-functional execution. Own resolution of critical yield and quality issues through containment, corrective actions, and prevention plans. Device Technology & Process Interaction Analysis Analyze device-level failure mechanisms and process sensitivities impacting ASIC functionality and yield. Evaluate design-process interactions affecting analog, mixed-signal, memory, high-speed I/O, and PCIe PHY performance. Partner with foundry teams to understand process variations, excursions, reliability risks, and technology limitations. Translate silicon learning into actionable design and process improvements. Advanced ASIC Design Interaction & Silicon Debug Lead root-cause investigations involving design-process interactions affecting SRAM, PCIe PHY, ONFI interfaces, SerDes, analog/mixed-signal circuits, and high-speed digital subsystems. Analyze silicon failures across transistor, circuit, block, die, package, and system levels. Drive post-silicon debug activities involving design teams, DFT, product engineering, quality,

Zoox is on an ambitious journey to develop a full-stack autonomous robotaxi solution, and freeways are the next frontier. We are looking for a Senior Staff or Principal Software Engineer who has played a significant role in removing the driver from an autonomous vehicle operating on freeways, and who can help Zoox navigate that same journey. You will bring deep technical expertise in a relevant autonomy domain — the specific domain is flexible — along with the hard-won judgment that comes from having taken a freeway driving program from supervised operation to driverless. This is a highly visible role with broad influence across the Autonomy organization. In this role, you will: Guide autonomy-wide initiatives toward driverless freeway operation, including setting the technical vision and strategy, building the roadmap, and driving cross-functional execution Identify the highest-risk gaps between our current freeway capabilities and driver-out readiness, and lead the engineering work to close them Develop algorithms that enable freeway driving capabilities, spanning architecture, design, implementation, integration, testing, and verification and validation Communicate technical trade-offs, risk assessments, and readiness recommendations to diverse stakeholders, including senior and executive leadership Mentor engineers across the freeway program and raise the bar for how we design, test, and validate high-speed autonomous driving Qualifications: 10+ years of industry software experience Demonstrated technical leadership of removing the human driver from an autonomous vehicle operating on freeways or highways Deep technical expertise in at least one autonomy domain, such as behavior/motion planning, perception, prediction, simulation, or systems engineering Proven ability to