Methodology Jobs

Java Software Engineer - Developer (Experienced and Senior) Company: The Boeing Company The Boeing Company is currently seeking Java Software Engineers – Developer (Experienced and Senior) to support our Advanced Ground Architecture team located in Herndon, Virginia, Colorado Springs, Colorado, Mesa, Arizona, Seal Beach, California and El Segundo, California. This position will focus on supporting the Boeing Defense, Space & Security (BDS) Software Engineering organization. The Advanced Ground Architecture (AGA) software team is a dynamic group of software engineers creating the future of Ground support with the extensibility and adaptability to be used across ALL Boeing programs. The software team is executing this vision through modern software technologies (Java, ReactJS, python, CI/CD pipelines) and methodologies (Scaled Agile). AGA is looking for self-motivated high performers to execute the large scope of Java development needed for the program's vision. The ideal candidates will provide software engineering functions for the design, development, and maintenance of complex, multi-tiered application software systems used to support the command and control of space vehicles. The software engineers will work day-to-day with system and test engineers in order to implement, test, and document new features and improvements for both web services and applications supporting distributed computing solutions. Position Responsibilities: Designs, develops, tests, and maintains software in an Agile execution that meets industry, customer, safety, and regulation standards throughout the end-to-end lifecycle Reviews, analyzes, and translates customer requirements into initial design and softwa

Lead Java Software Engineer - Developer Company: The Boeing Company The Boeing Company is looking for a Lead Software Engineer - Developer to join the Advanced Ground Architecture team located in Herndon, Virginia, Colorado Springs, Colorado, Mesa, Arizona, Seal Beach, California and El Segundo, California. This position will focus on supporting the Boeing Defense, Space & Security (BDS) Software Engineering organization. The Advanced Ground Architecture (AGA) software team is dynamic group of software engineers creating the future of Ground support with the extensibility and adaptability to be used across ALL Boeing programs. The software team is executing this vision through modern software technologies (Java, ReactJS, python, CI/CD pipelines) and methodologies (Scaled Agile). AGA is looking for self-motivated high performers to lead and execute the large scope of Java development needed for the program's vision. The ideal candidates will provide Java software development leadership for the Advanced Ground Architecture program, specifically the System Planning and Scheduling team. These positions will be responsible for accelerating complex java development, shepherding peer reviews for code merge requests at a faster cycle time, providing sub system leadership on key components, mentoring early and mid career software developers in AGA to be higher performers, and assisting P6 and Chief Engineering on architecture and software system engineering duties and decisions. These responsibilities are in addition to monitoring overall cost and schedule performance to meet or exceed expectations. Position Responsibilities: Oversees the design, deve

About the Team OpenAI’s People team hires, engages, and retains world-class talent to safely build and deploy AGI that benefits all of humanity. The People Analytics team helps leaders make better, evidence-based talent decisions. About the Role As a People Research Scientist, you will bring deep expertise in research design, measurement, experimentation, and applied data science to OpenAI’s most important People programs. You will design studies, evaluate people processes, and help leaders better empower employees, strengthen organizational systems, and deliver exceptional employee experiences. This is a high-ownership individual contributor role combining hands-on research, methodological leadership, and scalable people science capabilities. We’re looking for an experienced researcher who can turn ambiguous People questions into rigorous designs, validated insights, and actionable recommendations. This role is based in San Francisco, CA or Mountain View, CA, with occasional travel to our San Francisco office. What You’ll Do: Design rigorous research and evaluation strategies for recruiting, organizational health, manager effectiveness, employee experience, and talent outcomes. Apply advanced statistical modeling, machine learning, and research methods to inform program design, evaluate effectiveness, and quantify business impact. Partner with People Operations, data engineering, and people systems teams to define data requirements, improve data quality, establish documentation standards, and ensure research datasets are governed, reproducible, and privacy-preserving. Build scalable people science infrastructure, including self-service agentic tools, automated validation workflows, reusable research datasets and analytical pipelines. Develop research playbooks that establish rigorous standards for study design, measurement, validation, and documentation, enabling high-quality, repeatable, and scalable research across the organization. Communicate findings through c

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Position Overview This role focuses on using process and defect simulation methodologies to systematically identify defect root causes (true RC) and enable process window optimization . As part of the RDA / Yield Engineering organization, you will work on high-impact projects that connect process physics, simulation results, and manufacturing data to improve process capability and final product yield. This is an exciting opportunity for engineers passionate about linking simulation with real fab problems and turning modeling insights into measurable manufacturing improvements. Responsibilities Develop and apply process / defect simulation models to understand defect generation mechanisms across key wafer fabrication steps. Correlate simulation results with inline defect, EBI, process data, and yield indicators to identify true root causes of defects. Drive data-backed process optimization strategies to expand process windows and improve yield and reliability. Perform what-if simulations to evaluate the impact of process parameter changes, material variations, or equipment conditions. Partner with process, integration, and equipment engineers to translate simulation insights into fab-implementable actions . Lead or support defect reduction, yie

Job Title Lead Software Technologist I - UI Job Description Minimum required Education: Bachelor's / Master's Degree in Computer Science, Software Engineering, Information Technology or equivalent. Job title: Lead Software Technologist I Your role: Lead development of intuitive clinical user interface applications used by clinicians in high-acuity environments. Collaborate with UX teams and clinicians to ensure applications meet usability and safety requirements. Provide technical leadership across modern UI technologies and supporting C++ layers for embedded devices. Lead and mentor Platform development teams on software architecture, design patterns, and embedded systems best practices through daily hands-on collaboration. Lead and mentor application development teams on application services for physiological data visualization, and clinical decision support features. Establish and enforce quality standards, development methodologies, and coding practices that drive continuous improvement in software reliability and performance. Conduct rigorous code reviews and provide constructive technical feedback to ensure adherence to medical device software standards (IEC 62304, FDA regulations) Optimize application performance by identifying and resolving bottlenecks in resource-constrained embedded Linux environments. Drive the adoption of AI-enabled development tools and demonstrate measurable productivity improvements across the team. Collaborating with cross-functional teams including Product Management, QA, Regulatory, and other engineering leads to define and deliver features. Support software lifecycle management activities including sustaining engineering, defect resolution, and platform evolution.

We are now looking for a Senior SRAM Engineer within our Full Custom Memory (FCM) team! The FCM team designs specialized RAM implementations across NVIDIAs wide array of processing chips. Be it high speed, low power, multiport, we engage closely with processor architecture teams to build custom solutions across the entire NVIDIA silicon portfolio. Are you interested in designing circuits for the next generation of AI chips? Join a team of dedicated engineers developing the custom SRAM circuits that help power these chips. What you'll be doing: Design best-in-class SRAM circuits using state-of-the-art technology processes Optimize circuits for performance, area, and power Collaborate with mask designers to craft high quality and dense pitch-matched layout Verify functionality, electrical integrity, and robustness Improve/develop flows and methodologies to streamline design automation, data collection, and analysis to ensure working silicon What we need to see: BS/MS/PhD (or equivalent experience) in Electrical or Computer Engineering Minimum 12 years of circuit design experience Strong understanding of SRAM and memory design techniques and macro/block development Ways to stand out from the crowd: Self-motivation, attention to detail, clear data analysis and presentation skills Familiarity with industry tools such as Cadence Virtuoso for schematic and layout, SPICE simulators, waveform viewers Background with developing and using various flows and methodologies, in

Drupal Developer India Jaipur, Rajasthan Job Description: • Minimum 2+ years of experience in working on Drupal sites 7.x Or 8.x • Experience in developing front end technologies, including HTML, CSS, JavaScript, JSON, JQuery • Experience in Agile methodologies • Knowledge of GIT • Ability to write modules that create custom solutions to client problem • Knowledge of any one framework is must - Code Ignitor, Cake PHP, Laravel, Symphony

Manage site security operations in harmony with business objectives and Security Strategy Roadmap at major sites. • Protect enterprise-wide infrastructure to ensure business continuity, creating a safe environment for all • Employees and stakeholders and ensuring enhanced security and personal safety of “designated protected” • Address fraud & misconduct through a well-established framework to prevent, detect, respond, and refine strategies and methodologies. • Identify potential threats and calibration of risks from detailed security risk assessments to eliminate, reduce or mitigate risks. • Responsible for ensuring security and protection of tangible and intangible assets, at the site • Responsible for managing security related automation and infrastructure projects Source: Adani Group | Job ID: 50710

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

About Supabase Supabase is the Postgres development platform, built by developers for developers. We provide a complete backend solution including Database, Auth, Storage, Edge Functions, Realtime, and Vector Search. All services are deeply integrated and designed for growth. About the Role We’re looking for a Postgres Deployment Engineer to join our PostgreSQL team and help elevate our PostgreSQL offerings. You’ll work closely with the PostgreSQL team, playing an instrumental role in technical decision-making and refining internal methodologies. This role is ideal for someone who thrives in async, fast-paced environments and is excited about building developer tools that scale to millions. The focus of this role is owning the stability and deployment of our products. You will act as a bridge between product and infrastructure teams to improve the reliability of deployments and upgrades. You will have co-responsibility for builds and deployments via our public supabase/postgres GitHub repository, which bundles features into Docker images and AWS AMIs for cloud and local use. What You’ll Be Responsible For Package software into our supabase/postgres repo using Nix (with flakes), and help us transition our packaging from traditional to Nix packaging more over time. Manage PostgreSQL lifecycles, ensuring timely major, minor, and extension upgrades. Expand platform release systems to allow developers to increasingly self-service. Optimize CI/CD and tooling, specifically expanding GitHub Actions, team tooling, and testing/release approaches. Resolve production issues by proactively identifying and fixing problems in customer deployments. Maintain best practices and tests to ensure enhanced stability and decreased deployment risks. You Might Be a Good Fit If You Have 3+ years of experience with PostgreSQL and its ecosystem, including extensions and performance optimization. Are an Infrastructure Expert with proven experience in management, tooling, and optimization. Are p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. What’s Encouraged Daily: AI-First Engineering: Deploy AI tools (LLMs, code/RTL generation, spec parsing, waveform interpretation, layout engines) as default practice. Continuously identify automation opportunities and rearchitect workflows—specs, simulations, reviews, hand-offs—to be AI-consumable. Build prompt libraries, agents, and scripts that eliminate recurring manual patterns! AI Leadership: Champion AI adoption by evaluating emerging tools, running pilots, and publishing standard methodologies that measurably reduce cycle time or prove quality! Technical Ownership: Design and verify major IO/datapath blocks (receivers, serializer, clock distribution, equalizers, ZQ calibration, ONFI training, wave pipelines) to meet performance specs, using AI to accelerate exploration, sizing, and verification. Multi-functional Collaboration: Work with integration, design, and Apps teams to define interfaces and evaluate new specifications. Use AI to summarize discussions, reconcile specs, and quantify trade-offs. Mentorship: Document AI-augmented methodologies and teach engineers to work in an AI-first environment—not just which tools to use, but how to rethink engineering with AI. Minimum Qualifications: BS/MS in Electrical Engineering with 8+ years IC design experience Hands-on AI tool usage (LLM assistants, coding copilots, agentic workflows, ML-based EDA) with concrete examples of productivity or design impact Experience redesig

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Drive Cost and/or Max Out goals • Understand short-term and long-term Cost, Max Out goals within Front End and ensure alignment to corporate business goals. Initiate and drive cross-functional programs to achieve corporate business goals • Facilitate the definition of program scope, goals, deliverables, timeline and resource requirements in collaboration with sponsors and stakeholders • Manage the definition, refinement, and implementation of core methodologies and tools for business process including reporting • Drive delivery of IPP Goals Performance Deliver tactical support and program management • Establish structure and manage program dependencies, prioritize programs, track program milestone and deliverables • Enable program success through subject matter expertise • Deliver program proposals and regular progress reports • Identify potential road blocks, develop and execute resolution plans • Facilitate regular meeting cadence with key business partners • Engage with key stakeholders and leadership teams to assess program strengths and identify areas for improvement Communication • Conduct regular communication update to Sen

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role As an AI Accelerator Systems Software Technical Program manager at OpenAI, you will help bring our chips/system hardware roadmap to life, navigating an array of technical and partnership challenges. We’re looking for people excited to push the frontiers of computing by navigating technical explorations and are passionate about building. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Manage the end-to-end software development from design to implementation for our AI acceleration systems, working across technical, cross-functional and external stakeholders Lead planning and scheduling of AI system software designs with our strategic partners and vendors Coordinate and lead internal resources and communication for efficient interaction with partners and vendors. You might thrive in this role if you: Have experience as a software technical program manager for data center system products (server, GPU, TPU, networking, storage and so on) taking products from concept to volume in a data center environment ensuring the systems scale with high quality Know end-to-end software development program management techniques from concept, design, production, deployment into the data center Want to help design some of the world’s largest supercomputing systems, working at the edge of complex hardware challenges Enjoy working with and enabling world-clas

About the Team Our Robotics team is focused on unlocking general-purpose robotics and pushing towards AGI-level intelligence in dynamic, real-world settings. Working across the entire model stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the constraints of physical systems to improve people's lives. About the Role We are seeking a lead thermal simulation engineer to help accelerate the design and development of next-generation robotic systems through modeling, simulation, and analysis. You will work closely with mechanical, electrical, controls, and robotics engineers to evaluate designs before hardware is built, identify risks early, and guide critical architecture decisions. This role spans structural and thermal analysis and design across robotic subsystems including actuators, mechanisms, structures, electronics, and integrated systems. You will develop simulation workflows that improve engineering velocity, increase confidence in design decisions, and help us build more capable, reliable, and manufacturable robotic platforms. This role is based in San Francisco, CA. This role will be expected to be in office 4 days per week and offer relocation assistance to new employees. In this role, you will: Perform thermal simulations to assess heat generation, cooling strategies, thermal interfaces, and system-level thermal performance Partner with mechanical, electrical, and controls engineers to influence design decisions early in development Build simulation models to evaluate robotic actuators, transmissions, mechanisms, structures, soft goods, and integrated assemblies Correlate simulation results with physical testing and develop methodologies to improve model accuracy Support architecture trade studies by evaluating design concepts before hardware is built Develop simulation workflows, standards, and best practices that scale across the robotics o

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de