Package Engineering Engineer Jobs

Utilize the link below to copy and paste your new JD from: [Make a Copy] OKX Job Description OR Use the Template Below: OKX will be prioritising applicants who have a current right to work in Hong Kong, and do not require OKX's sponsorship of a visa. Who We Are At OKX, we believe that the future will be reshaped by crypto, and ultimately contribute to every individual's freedom. OKX is a leading crypto exchange, and the developer of OKX Wallet, giving millions access to crypto trading and decentralized crypto applications (dApps). OKX is also a trusted brand by hundreds of large institutions seeking access to crypto markets. We are safe and reliable, backed by our Proof of Reserves. Across our multiple offices globally, we are united by our core principles: We Before Me , Do the Right Thing , and Get Things Done . These shared values drive our culture, shape our processes, and foster a friendly, rewarding, and diverse environment for every OK-er. OKX is part of OKG, a group that brings the value of Blockchain to users around the world, through our leading products OKX, OKX Wallet, OKLink and more. About The Opportunity What You’ll Be Doing What We Look For In You Nice-To-Haves Perks & Benefits Competitive total compensation package L&D programs and education subsidy for employees' growth and development Various team building programs and company events Wellness and meal allowances Comprehensive healthcare schemes for employees and dependants More that we love to tell you along the process! Please note that Hong Kong is a group-level service hub, and OKX does not carry on a business of operating a virtual asset trading platform in Hong Kong. Notice: All official OKX vacancies are published on this website. While roles may appear on selected third-party platforms from time to time, information on other sites may be inaccurate or outdated. If in doubt

About us Sierra is the leading platform for customer-facing AI agents, working with many of the world's biggest brands — including The GAP, Rocket Mortgage, SoFi, Sutter Health, and SoftBank — to transform how they serve customers and grow their businesses. We are primarily an in-person company based in San Francisco, with growing offices across North America, Europe, and Asia. We are guided by a set of values that are at the core of our actions and define our culture: Trust, Customer Obsession, Craftsmanship, Intensity, and a commitment to balancing Family along the way. These values are the foundation of our work, and we are committed to upholding them in everything we do. Our co-founders are Bret Taylor and Clay Bavor . Bret currently serves as Board Chair of OpenAI. Previously, he was co-CEO of Salesforce (which had acquired the company he founded, Quip) and CTO of Facebook. Bret was also one of Google's earliest product managers and co-creator of Google Maps. Before founding Sierra, Clay spent 18 years at Google, where he most recently led Google Labs. Earlier, he started and led Google’s AR/VR effort, Project Starline, and Google Lens. Before that, Clay led the product and design teams for Google Workspace. About the Retail Team The Retail team on Agent Engineering supports some of the largest and most storied consumer brands in the world – including Gap, Wayfair, Sonos, and ADT. Together, we’re reinventing what commerce looks like in this new, AI-first era. Our customers rely on us to not only deliver novel experiences, but also host hundreds of millions of shopper and vendor interactions across web, app, phone, and in-store channels every year. Our team supports our customers’ customers in the moments that matter – whether that's guiding a shopper to the right product during a limited drop or a Black Friday surge, locating a package that never arrived, or troubleshooting an appliance that stopped working. Always true to each brand’s voice, we create seamless

Utilize the link below to copy and paste your new JD from: [Make a Copy] OKX Job Description OR Use the Template Below: OKX will be prioritising applicants who have a current right to work in Hong Kong, and do not require OKX's sponsorship of a visa. Who We Are At OKX, we believe that the future will be reshaped by crypto, and ultimately contribute to every individual's freedom. OKX is a leading crypto exchange, and the developer of OKX Wallet, giving millions access to crypto trading and decentralized crypto applications (dApps). OKX is also a trusted brand by hundreds of large institutions seeking access to crypto markets. We are safe and reliable, backed by our Proof of Reserves. Across our multiple offices globally, we are united by our core principles: We Before Me , Do the Right Thing , and Get Things Done . These shared values drive our culture, shape our processes, and foster a friendly, rewarding, and diverse environment for every OK-er. OKX is part of OKG, a group that brings the value of Blockchain to users around the world, through our leading products OKX, OKX Wallet, OKLink and more. About The Opportunity What You’ll Be Doing What We Look For In You Nice-To-Haves Perks & Benefits Competitive total compensation package L&D programs and education subsidy for employees' growth and development Various team building programs and company events Wellness and meal allowances Comprehensive healthcare schemes for employees and dependants More that we love to tell you along the process! Please note that Hong Kong is a group-level service hub, and OKX does not carry on a business of operating a virtual asset trading platform in Hong Kong. Notice: All official OKX vacancies are published on this website. While roles may appear on selected third-party platforms from time to time, information on other sites may be inaccurate or outdated. If in doubt

Senior Container Security Engineer – CVE Remediation & Image Hardening About the Role We are looking for a hands-on Senior Container Security Engineer to lead vulnerability remediation and image hardening across Linux-based container environments. This role focuses on deep operating system and container security engineering rather than simple vulnerability scanning. You will analyze, remediate, rebuild, harden, and continuously optimize container images used in modern cloud-native platforms. You will work closely with platform engineering, DevOps, infrastructure, and security teams to build automated remediation pipelines, reduce the attack surface, and deliver production-ready hardened images. What You’ll Do - Own end-to-end CVE remediation across Linux-based container images. - Analyze vulnerabilities across OS packages, libraries, runtimes, and dependencies. - Patch, rebuild, validate, and maintain hardened container images at scale. - Reduce attack surface by removing unnecessary packages, binaries, services, and dependencies. - Build and scale automated remediation pipelines for continuous image patching. - Improve image security posture while minimizing operational disruption. - Generate, validate, and maintain SBOMs to support supply chain visibility and compliance. - Integrate remediation workflows into CI/CD and GitOps pipelines. - Optimize image size, startup performance, and operational efficiency. - Research emerging Linux, container, Kubernetes, and software supply chain threats. - Troubleshoot complex dependency, package compatibility, and runtime security issues. - Help define internal standards for hardened images and secure software delivery. What You Bring - 5+ years of experience in Linux systems engineering, platform engineering, DevSecOps, security engineering, or SRE. - Deep understanding of Linux distributions (Debian, Ubuntu, Alpine, RHEL). - Strong hands-on experience with Docker, Kubernetes, and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Position Summary As an APTD MTS (Member of Technical Staff) based in Taiwan, you will lead and develop the IoT engineering team delivering Industrial IoT (IIoT) and machine vision solutions to support advanced packaging technology development and factory enablement. You will set technical direction and priorities, drive execution from proof-of-concept through deployment, and build scalable, secure solutions that improve quality, productivity, and early risk detection. You will partner cross-functionally to translate manufacturing needs into measurable signals, robust data pipelines, and actionable insights, while building a culture of safety, accountability, and continuous learning. Key Responsibilities Lead, coach, and develop the IoT engineering team; set clear expectations, provide regular feedback, and build growth plans aligned to APTD needs. Own team execution: define goals/KPIs, prioritize the IoT roadmap, assign ownership, and ensure high-quality, on-time delivery from concept to factory deployment. Drive end-to-end IIoT solution development: sensing strategy, edge compute, connectivity, data ingestion/storage, monitoring, and sustainment (including data quality and traceability). Drive machine vision solutions: guide hardware selection (cameras/optics/lighting), image acquisition strategy, algorithm approach, performance validation, and deployment readiness. Partner with process, equipment, automation, quality, and IT/data platform stakeholders to tra

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description Industrial Engineer As Industrial Engineer under Package Development & Engineering (PDE), you will be responsible to develop, align and coordinate with cross functional to ensure effective Capacity Modeling. In this role, you will need to work with Technology Development, Key Equipment Group and other stakeholder from site to support Micron Business Objective. Responsibility Responsible for EPT related topic, Consolidate & align MOR/UPH/EPT improvement across Micron Site and Central Team Engage with manufacturing sites, and Central Teams to provide technical direction and maintain alignment for Engineering Tool time and space related between manufacturing site and Technology Development <span s

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Inspection Technology & Equipment Ownership Manage advanced inspection and metrology platforms throughout package development and manufacturing. Develop technology roadmaps and capability strategies to meet future packaging requirements. Drive equipment lifecycle management, capacity planning, and technology insertion activities. Equipment Qualification & Deployment Lead tool installation, qualification (TIQ), release, and production readiness activities. Establish equipment acceptance criteria, qualification methodologies, and deployment plans. Drive tool-to-tool matching and network standardization initiatives. Defectivity Engineering & Yield Improvement Develop inspection solutions to detect, monitor, and reduce critical defect mechanisms. Set up defect metrics, observa

Job Details: Job Description: Join Intel's Silicon and Platform Engineering Group (SPE) as an Exempt Tech Contract Employee, The Role and Impact :As a Power Integrity Engineer, you will play a pivotal role in ensuring Intel's platforms and products meet the highest standards of performance and reliability. This position offers you the opportunity to work on cutting-edge technologies, designing and optimizing power delivery networks for complex high-speed platforms, boards, packages, and silicon. Your contributions will directly impact Intel's ability to deliver industry-leading solutions to its customers, driving innovation in power integrity and enhancing the performance and functionality of our silicon and systems. Join us to tackle exciting challenges and create impactful solutions that push technological boundaries. The primary responsibilities for this role will include, but are not limited to: Develop and analyze power delivery networks, including 2D and 3D model extraction and noise analysis across die/C4 bumps, silicon, package, sockets, and boards. Define power grid specifications and power and area targets to achieve optimal balance between power integrity and performance. Design test structures, electrical analysis methodologies, and verification plans to address power integrity challenges. Perform measurements to characterize power noise profiles across frequency, ground bounce, and other critical metrics, verifying power delivery networks post-design. Correlate measurements back to presilicon analysis and estimations for improved accuracy. Apply expertise in power integrity design and tradeoffs to guide simulations of power networks and physical implementations for packages and platforms. Ensure on-die power noise meets system-on-chip (SoC) functionality an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will contribute to the design and delivery of next‑generation memory products by working across circuit design, layout, and validation. You will apply simulation, modeling, and verification skills to improve

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role Overview The ASIC Test Engineer is responsible for test program development, silicon validation, yield analysis, and production test optimization for advanced ASIC/SSD controller products. This role supports both NPI and HVM phases, driving fast ramp, robust quality, and cost-effective test solutions across wafer sort and final test. Key Responsibilities Develop and debug ATE test programs for wafer sort and final test (probe to package) to support silicon bring-up and production ramp. Drive yield analysis, failure characterization, and root cause investigation to accelerate yield improvement and ensure product quality. Collaborate with design, product engineering, reliability, and OSAT teams to resolve test and silicon issues across the product lifecycle. Optimize test coverage, test time (TTR), and cost through test content development, guardband tuning, and screening strategy improvements. Support hardware bring-up including probe cards, load boards, and tester configurations to ensure stable manufacturing operations. Enable efficient NPI execution by developing scalable test solutions and improving cycle time from bring-up to HVM. AI/Advanced Data Capability Apply AI/ML and data-driven methodologies to enhance yield analysis, anomaly detection, and failure classification. Leverage AI-assisted tools (e.g., code generation, debug automation, data analytics platforms) to improve engineering productivity and debug cycle time.<br

1891 Signal Integrity Measurement Engineer Location: Austin About the Role Validate signal integrity (SI) and power integrity (PI) for advanced compute platforms, focusing on hands-on measurement, electrical compliance, troubleshooting, and simulation correlation. Key Responsibilities Develop measurement plans and design of experiments (DOE) for board-to-board, cable, backplane, blade-, and rack-level interconnects. Measure scattering parameters (S-parameters), insertion loss, return loss, impedance, crosstalk, eye diagrams, jitter, timing margins, and bit error rates. Design printed circuit board (PCB) test fixtures; perform calibration, de-embedding, and electrical compliance testing against interface specifications and customer requirements. Correlate measurements with simulations and troubleshoot issues with silicon, package, board, and system teams, interconnect vendors, and original design manufacturers (ODMs). Prepare validation and compliance reports covering methods, pass/fail results, performance margins, findings, and recommendations. Required Qualifications Hands-on expertise with vector network analyzers (VNAs), including performance network analyzers (PNAs); time-domain reflectometers (TDRs); bit error rate testers (BERTs); and high-speed oscilloscopes. Strong SI/PI fundamentals and experience with fixture characterization, repeatable measurements, DOE, and electrical compliance testing. Strong written and verbal communication skills for technical reporting and cross-functional collaboration. Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field. Preferred Qualifications Data center or hyperscale hardware experience; Python or MATLAB for measurement automation and analysis; familiarity with simulation tools and thermal or mechanical effects on SI/PI. Tools / Technologies Peripheral Component Interconnect Express (PCIe) generations 4/5/6, Ethernet, Double Data Rate (DDR) memory, serializer/deseria

NVIDIA is seeking an a PCB Library Engineer to join our PCB Design Infrastructure team. In this role, you will help develop and maintain the PCB library assets used across NVIDIA's Data Center, AI, Networking, Automotive, and Graphics products. Working alongside experienced PCB designers, library engineers, mechanical engineers, manufacturing engineers, and component engineers, you will create and validate component footprints, schematic symbols, mechanical components, panel definitions, and other critical design assets that enable successful product development. This position provides an excellent opportunity to build expertise in PCB design, manufacturing, component engineering, and design automation while supporting some of the most advanced computing platforms in the world. What you'll be doing: Develop PCB footprints, padstacks, schematic symbols, and mechanical library content using Cadence PCB design tools. Review component datasheets, package drawings, and engineering specifications to create accurate design libraries. Support library verification, release, and documentation processes. Partner with PCB design, mechanical engineering, manufacturing engineering, and operations teams to resolve library-related issues. Learn and apply industry standards, including IPC requirements, DFM, DFA, and DFT principles. Support quality initiatives to ensure library content is accurate, manufacturable, and scalable. Participate in continuous improvement and automation efforts within the library environment. Develop a strong understanding of PCB fabrication, assembly, and component technologies. What We Need to See: BS degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, Manufacturing Engineering, or a related field or equivalent experience. <p

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking a Package Reliability Engineer to lead reliability engineering for advanced packages used in high-performance AI and computing systems. The primary focus of this role is to assess package level mechanical and thermal reliability risks and apply thermal and mechanical modeling to optimize package design, material selection, and assembly processes. The engineer will also develop reliability test plans with external partners, identify failure mechanisms, perform root-cause analysis, and recommend practical corrective actions. In this role, you will assess package reliability risks from early architecture development through product qualification and high-volume manufacturing. You will work closely with package design, silicon design, system engineering, manufacturing, and ASIC partners to predict package behavior, develop qualification strategies, resolve reliability issues, and improve overall package robustness and lifetime. In this role you will: Lead reliability test plan and assessments for advanced HPC packages, including risk identification, potential failure-mechanism analysis, root-cause investigation, mitigation planning, and corrective-action development. Drive reliability-focused package design optimization based on thermo-mechanical modeling to improve package reliability, power integrity, thermal performance, mechanical robustness, and platform scalability. Develop, validate, and apply package reliability models and lifetime-prediction

1671 About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design , with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication. Key Responsibilities End-to-end signal integrity analysis for blade- and rack-level system architectures. Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI , I2C, etc . and related interconnects. Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE , or similar. Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes . Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology. Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance. Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions. Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware. Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field . Strong experience in signal integrity for high-speed digital systems. Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes . Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and cro

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Senior High Bandwidth Memory (HBM) Electrical Failure Analysis (EFA) Engineer Job Description As a Global Quality (GQ) High Bandwidth Memory (HBM) Electrical Failure Analysis (EFA) Engineer on the DRAM/Emerging Memory Quality and Reliability Assurance team (DEMQRA) at Micron Technology, Inc., you will be responsible for the electrical characterization and electrical failure analysis (EFA) of all HBM products. You will need to distinguish whether it is package or device related failures. Preferably, you are equipped with knowledge of DRAM functionality, process, test program and device necessary for making solid judgment. You will also use a variety of test tools including the uMate tester, Merlin, Mongoose SM3 , Prober, CAD layout tool, and a variety of technical drawings and schematics to perform detailed characterization on HBM products. You will record and categorize failures in order to determine failure mechanisms and characteristics. In this role, you will communicate with various engineering groups, assist lab users with equipment setup and interpretation of data, and maintain critical EFA knowledge database. You will also be expected to apply AI to seek ways to improve the EFA process in order to reduce test time, increase throughput, and increase f