Packaging Engineer Flip Chip Jobs

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize flip chip attach processes including bump formation, placement, reflow, and underfill for high-performance semiconductor packages. Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps) and substrate pad finishes for robust interconnect performance. Drive package integration from die to substrate, ensuring alignment, coplanarity, and yield optimization. Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding, head-in-pillow, and interconnect defects. Collaborate with substrate vendors, OSATs, and internal teams to define design rules (pad pitch, bump pitch, keep-outs, stack-ups). Lead process development for reflow profiles, flux selection, cleaning, and underfill dispense/cure. Perform root cause analysis of assembly and reliability failures using cross- sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manufacturing teams to ensure robust package performance from concept through high-volume production. Required Technical Skills: Strong experience in flip chip packaging and assembly processes for semiconductor devices. Deep understanding of bumping technologies (solder bumps, Cu pillar, micro- bumps) and UBM/metallization systems. Experience with underfill materials, dispense techniques, flow behavior, and cure processes. Understanding of thermo-mechanical behavior in flip chip assemblies (CTE mismatch, warpage, solder

We’re looking for a hands-on process and materials engineer to own wafer level molding and underfill processes, material qualification, and assembly integration across development and manufacturing. Summary: Seeking an experienced engineer to lead wafer level mold and underfill process development for advanced semiconductor packages (fan-out wafer level packaging, 2.5D/3D, chiplet). This role spans mold compound and underfill material selection and qualification, wafer level molding and encapsulation processes, underfill dispense and cure, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize wafer level molding processes including compression molding, transfer molding, and mold underfill (MUF) for fan-out and advanced heterogeneous packages. Own mold compound and underfill material selection and qualification, including evaluation of filler content, CTE, modulus, Tg, viscosity, and moisture uptake to meet thermo-mechanical and reliability requirements. Drive underfill process development including capillary underfill (CUF) dispense strategies, flow and void optimization, and cure profile development for high-density flip chip and chiplet assemblies. Evaluate and mitigate assembly risks including warpage, delamination, void formation, bleed-out, mold flash, and filler settling; define process windows and controls to ensure repeatable yield across wafer and panel formats. Collaborate with OSATs and material suppliers to qualify mold and underfill materials, define dispense and cure equipment requirements, and manage process transfers into production. Lead characterization of mold and underfill material properties (viscosity, gel time, cure kinetics, adhesion, CTE, modulus) and correlate material behavior to process outcomes and package reliability. Work closely with thermal mechanical modeling teams to model solder joint reliability of bump interconnects with va

About the Role You will contribute to and own aspects of the Volantis A-0 and A-1 package. We are interested in both people with package design as well as package process development backgrounds Our end goal has challenges to overcome in warpage, CTE mismatch, thermomechanical aspects, assembly speed and more. We're building a wafer-scale package with both silicon and compound semiconductor dies sitting together at very high TDP. This creates both unique challenges and opportunities. The end result is breaking the memory wall, enabling a new era of AI, and a platform that scales another 1-3 orders of magnitude. What We Look For Ability to think from first principles about novel problems- not just applying existing solutions outside of their range of application. What works for 5x reticle platforms may not work for 56x reticle platforms Design or process development of complex packages Nice to Have: Experience with heterogeneous material assemblies Experience with high-TDP packages Experience with compound semiconductor assemblies Experience with co-packaged optics Ability to work with architects to co-design system architecture and package design Experience with interposer platforms such as CoWoS, CoWoS-L, CoWoS-R, EMIB, FoCoS, FoCoS-Bridge, etc Experience with flip-chip integration, especially mass reflow, TCB & LAB Experience with large scale (>50x50mm) substrates Compensation Package: Competitive Base salary + Significant Equity Stake. You'll be well compensated while also owning a piece of the outcome. California Pay Range: $250K-$400K

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: A senior advanced assembly technology development engineer is responsible for introducing new technology to enable next generation packaging. This position engaged latest stacking/flip chip technology, advance packaging material and work on new process set up, process/ packaging characterization and process transfer from TD phase to high volume production to meet development milestone. This position required high motivation and operation skill to build DOE sample and fulfill customer requirement sample as well as cooperate with Material engineer, Bumping, PI, NPI, quality and manufacturing team to ensure process transfer successfully. Responsibilities Explore new technology on semiconductor industry such as flip chip, TCB and hybrid bonding process equipment and packaging material. Provide plan and resource requirement to enable new technology. Set up DOE plan and execute. Build sample and perform data analysis skill. Lead efficiency trouble shooting skill to improve process. Prepare documentation for process transfer from TD to HVM Review process stability by FDC, SPC and test result. Self-motivated and capable of working independently, proactively identifying opportunities and driving projects with minimal direction. <span

We take play seriously. We’re looking for curious adventurers ready to find their party, fueled by imagination and drive to build what’s never been built before. At Hasbro and Wizards of the Coast, you’ll collaborate with passionate teams to reimagine our iconic brands and create experiences that spark joy, connection, and community through the magic of play. This is your chance to shape legendary play that lasts a lifetime. Purpose of Role • Drive packaging structural simplicity whereas product protection is a primary goal of packaging box. • Oversee packing processes of Hasbro’s products and fully engaged with new packaging designs or improving existing ones to appeal consumer in terms of packaging structure design, quality and cost. • Drive strategic next generation materials, engage in hands-on project-based work, and establish key material suppliers’ relationships with a sharp focus on material and process sustainability. Key responsibilities include • Review different types of packaging that commonly applied in Hasbro, design and develop packaging solutions that is safe and cost-effective. • Supports structural packaging initiatives, such as process improvements, material qualification, manufacturing and cost improvements, and sustainability. • Maintain knowledge of industry trend, development and innovation in paper & cardboard materials and printing technology. Act as a SME to educate internal engineers for right use of packaging material, tackle packaging problem in development and manufacturing stage. Years of Experience Required • Minimum 2 years of relevant work experience with consumer product manufacturing industry. • Demonstrate working knowledge of technical packaging structure design, with good awareness of packaging construction development, materials and production technologies, i.e. packaging manufacturing, printing and converting process. Technical Skills Requirement • Bachelor’s degree in Engineering, Material Science, Packag

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out). This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities Own end-to-end bump interconnect development for both ubump (micro-bump) and C4 processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip attach for high-performance semiconductor packages. Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys) interconnects, including UBM selection and pad finish specifications for both chip-side and interposer capture pads. Develop and own design rules for bump interconnects including pitch, bump diameter, standoff height, keep-outs, and land pad geometry for both the chip side and interposer or substrate capture pads. Lead RDL (redistribution layer) process development including electroplating of Cu RDL traces, via fills, and pad finishes; define RDL design rules for line/space, via diameter, and layer stack-up to meet electrical and reliability requirements. Collaborate with OSATs and bumping foundries to qualify ubump and C4 bumping processes, drive design rule alignment, and manage process transfers into production. Evaluate and mitigate bump interconnect assembly risks including non-wet opens, voiding, head- in-pillow, intermetallic growth, and joint fatigue failures across both ubump and C4 interconnect types. Perform root cause analysis of assembly and reliability failures using cross-sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manu

We take play seriously. We’re looking for curious adventurers ready to find their party, fueled by imagination and drive to build what’s never been built before. At Hasbro and Wizards of the Coast, you’ll collaborate with passionate teams to reimagine our iconic brands and create experiences that spark joy, connection, and community through the magic of play. This is your chance to shape legendary play that lasts a lifetime. Purpose of Role • Drive packaging structural simplicity whereas product protection is a primary goal of packaging box. • Oversee packing processes of Hasbro’s products and fully engaged with new packaging designs or improving existing ones to appeal consumer in terms of packaging structure design, quality and cost. • Deliver insights of new paper-making methods such as recycling paper, new techniques for shaping and forming paper, and new materials for use in paper-based products. • Drive strategic next generation materials, engage in hands-on project-based work, and establish key material suppliers’ relationships with a sharp focus on material and process sustainability. Key responsibilities: • Review different types of packaging that commonly applied in Hasbro, design and develop packaging solutions that is safe and cost-effective. • Develop and implement quality control procedures to ensure consistent product quality such as paper, coating, inks and adhesives. • Supports structural packaging initiatives, such as process improvements, material qualification, manufacturing and cost improvements, and sustainability. • Maintain knowledge of industry trend, development and innovation in paper & cardboard materials and printing technology. Act as a SME to educate internal engineers for right use of packaging material, tackle packaging problem in development and manufacturing stage. • Reviewing competitors’ products and pricing to understand market trend and actively connect with Global printers to keep up-to-date packaging design

What We're Looking For: We're looking for photonics packaging engineers to contribute to, and own aspects of the A-0 and A-1 packages. This role bridges the classically divided photonics and advanced packaging skillsets, and thus is an unique point in our team. Ideal Background: Experience with integrated photonics package assemblies with multiple dies Experience with integrated circuit MCM assemblies with multiple heterogeneous materials, including compound semiconductors Understanding of photonics concepts, such as mode field diameters, mode mismatch, polarization, etc. Nice to Have: Experience with large device count photonic assemblies Experience with clear underfill Experience with high density fiber attach Experience with large substrate size photonic MCM assemblies Hands-on experience with PIC design

Title: AI Application Packaging Engineer Location: Andheri (East), Mumbai Reports to: Service Director ABOUT BLENHEIM CHALCOT: As part of the Blenheim Chalcot portfolio, we benefit from the expertise, infrastructure, and scale of the leading global venture builder. With over 25 years of experience creating and growing SaaS businesses powered by Generative AI, Blenheim Chalcot has built 60+ ventures across sectors such as financial services, education, health, and marketing. Our global ecosystem—including Scale Space in London, the Rajasthan Royals in Mumbai, and a go-to-market base in Austin—enables us to access world-class talent, tools, and support to accelerate our growth and build a market-leading business. THE ROLE: We’re looking for an AI-first ITS Engineer with strong Application Packaging expertise to join our growing team at Agilisys. In this role, you’ll work across Application Packaging, Endpoint Management, Cloud Deployment, and Automation, helping modernise IT operations through AI-driven and scalable solutions. This is an opportunity to work in a fast-paced environment where automation, innovation, and operational efficiency are at the core of what we do. ABOUT YOU: Must-Have's 5+ years of hands-on experience with SCCM and/or Microsoft Intune for application packaging, deployment, and endpoint management. Strong experience with PowerShell scripting and a good understanding of Windows Registry, File System internals, and deployment workflows. Experience managing application packaging, deployment, patching, and remediation processes in enterprise environments. Exposure to vulnerability management and patch lifecycle activities using tools such as WSUS, Active Directory, or endpoint security solutions. An AI-first mindset with interest or experience leveraging Generative AI tools to improve efficiency across packaging, testing, deployment, troubleshooting, and operational tasks. Hands-on experience using automation or AI-assisted tools

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. As part of Packaging Design Team, you will need to think about how to make the perfect unboxing experience for users, keep the safety for transportation, out of the box, break impossibility, and be open to discussion in pursuit of perfection.We don’t just expect you to build products simply but to be proud of what we do. Are you ready to embrace challenges in a fast-paced organization? Join UI, refresh us with your crazy but creative ideas, and make a great impact on the world together! Responsibilities (What he/she will do after join UI): Primarily focus on improving MP packaging design. Modify the packaging structure to enhance the unboxing experience and reduce costs simultaneously. Review samples, DFM, and SOPs. Ensure the structure passes the reliability test. Internal: Work closely with Packaging Designers & Packaging Design PMs. External: Work closely with CMs & Suppliers. Minimum Qualifications (MUST-haves) : Logical thinking / Proactive personality. Effective communication and time management skills. 3+ years of experience in development of packaging structure design. Experienced using 2D: AutoCAD Experienced using 3D: Rhino or Solidworks or ProE Knowledge of material processing for pulp tray, cardboard, blister, gift box, carton and all types of printing processes. Knowledge of a wide variety of packaging

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a hands-on Manufacturing Engineer to own the manufacturing interface between package design, semiconductor assembly, package test, board assembly, and final product integration. This role is focused on making advanced packages manufacturable and transferable from design engineering into qualified OSAT processes and downstream board/system assembly. You will work closely with Packaging Engineering, Silicon Manufacturing and Test, Quality, Supply Chain, PCB/board design, and external partners such as substrate suppliers, OSATs, test houses, and contract manufacturers. The ideal candidate understands how package decisions—such as package size, substrate construction, bump and ball design, warpage, underfill, materials, and assembly location—affect package yield, package test, PCB footprint and stencil design, SMT assembly, and final product readiness. This role is remote based out of Taiwan but requires close engagement with regional OSATs, foundry/test partners, contract manufacturers, and Tenstorrent engineering teams across multiple time zones. Regular on-site presence at partner factories is expected during qualification, commissioning, build, and ramp activities. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and of

Silicon Packaging Design Engineer — Arizona, Phoenix. Apply via Workday.

Senior Packaging Technical Engineer - Hardware — 3 Locations. Apply via Workday.

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking a Package Reliability Engineer to lead reliability engineering for advanced packages used in high-performance AI and computing systems. The primary focus of this role is to assess package level mechanical and thermal reliability risks and apply thermal and mechanical modeling to optimize package design, material selection, and assembly processes. The engineer will also develop reliability test plans with external partners, identify failure mechanisms, perform root-cause analysis, and recommend practical corrective actions. In this role, you will assess package reliability risks from early architecture development through product qualification and high-volume manufacturing. You will work closely with package design, silicon design, system engineering, manufacturing, and ASIC partners to predict package behavior, develop qualification strategies, resolve reliability issues, and improve overall package robustness and lifetime. In this role you will: Lead reliability test plan and assessments for advanced HPC packages, including risk identification, potential failure-mechanism analysis, root-cause investigation, mitigation planning, and corrective-action development. Drive reliability-focused package design optimization based on thermo-mechanical modeling to improve package reliability, power integrity, thermal performance, mechanical robustness, and platform scalability. Develop, validate, and apply package reliability models and lifetime-prediction

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