Physical Therapist Assistant Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Administer and support Lenel OnGuard access control systems. Manage and maintain Milestone XProtect video management systems. Troubleshoot and resolve hardware, software, database, network, and integrated security system issues. Support CCTV, access control, visitor management, video analytics, and related security technologies. Collaborate with IT, Facilities, Engineering, Security Operations, and external integrators. Lead or participate in system expansions, upgrades, migrations, commissioning, and modernization projects. Develop technical documentation, standards, and operational procedures. Support investigations through access control and video system data analysis. Drive standardization, lifecycle management, and continuous improvement of physical security technologies while ensuring systems, configurations, and operational processes align with global security standards, architecture requirements, and enterprise best practices. Partners with key team members to supervise data and continuously improve critical metrics, leveraging Generative AI insights where applicable. Required Experience 8+ years supporting enterprise physical security systems. Hands-on experience with: Lenel OnGuard Access Control Milestone XProtect VMS CCTV, card access, and integrated security systems Experience supporting Windows Server environments and SQL databas

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role Data Center Security Engineering (DCSE) secures Anthropic's data center footprint; this role covers how the sites are designed and built to be secure. Much of that footprint is designed and built with partners, so a site's security is decided early: in what Anthropic hands the people who build it, and in how rigorously the delivered systems are tested against it. You'll design and specify the physical security systems for a site: perimeter and vehicle barriers, intrusion detection, video, security lighting, and the site penetrations and utility entry points that bypass them. Design firms and integrators produce the site drawings and install; you specify, review, and verify. You'll write the performance requirement and verification method behind each control, review every site design against them at each stage with redlines a design team can act on, test in the field that what was built performs as specified, and re-verify post-acceptance changes. This is a foundational role. You'll own Anthropic's physical security reference design package (typical details, reference drawings, schedules, and test procedures) in the form partners build from, and keep it current against each site's threat basis and the sites actually being built. You'll set the technical position for a site and decide what applies where; where a requirement can't be met as written, you'll engineer the compensating control and document the deviation. You'll work with the rest of DCSE, with Anthropic's design, construction, and real estate counterparts, and directly with the vendors who build to the package. We use Claude throughout our engineering workflow

Job Details: Job Description: The Role and Impact As a Physical Design Engineer, you will play a critical role in driving the development of cutting-edge technologies at Intel. You will work hands-on to deliver high-performance physical designs, ensuring the successful integration of advanced semiconductor technologies. Your work will directly impact Intel's product innovation, addressing complex challenges in power, performance, and area optimization to shape the future of computing architectures. From synthesis to sign-off, your contributions will enable Intel to meet ambitious design goals and deliver transformative solutions to the market. Business Group This role is part of Intel's Corporate Technology Office (CTO), a dynamic group dedicated to advancing the company's technological leadership and innovation. The group focuses on developing foundational technologies, architectures, and methodologies that drive Intel's product roadmap and enable breakthrough computing solutions. Collaborating with cross-disciplinary teams, the CTO plays a pivotal role in delivering impactful designs that support Intel's broader mission of creating world-changing technology. Key Responsibilities - Drive RTL-to-GDS design convergence using advanced synthesis and place-and-route tools targeting performance, power, and area (PPA) goals. - Deliver block-level physical design, including closure of backend flows, electrical requirements, and enhancing silicon yield. - Collaborate with CAD and physical design methodology teams to adopt industry-leading tools and optimizations for custom designs. - Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification. - Debug timing, EM/IR, LVS, and DRC violations, and driv

Senior Engineer – IC Design (Physical Design - PV/Power/EM/IR Drop Engineer) — Hyderabad. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Physical Design team is responsible for implementing advanced High Bandwidth Memory (HBM) SoC and base die designs that enable next-generation AI, high-performance computing, and data center solutions. The team collaborates across architecture, RTL, verification, DFT, and signoff engineering to deliver high-performance, power-efficient silicon while developing innovative design methodologies and automation solutions. As an SoC Physical Design Intern on the HBM team, you will work alongside experienced engineers to support the implementation of advanced HBM SoC designs. You will gain hands-on experience with physical design methodologies, timing analysis, signoff flows, and automation while contributing to the development of next-generation memory products that power AI and high-performance computing applications. Responsibilities Support the physical implementation of SoC design blocks, including floorplanning, placement, clock tree synthesis, routing, and physical optimization activities. Analyze timing, power, area, congestion, and physical verification results to find opportunities for design improvement and optimization. Assist with static timing analysis, timing closure, and debugging across multiple operating modes and process corners. Develop and enhance automation tools, scripts, reports, and workflows using Python, Tcl, shell scripting, and AI-assisted solutions. Collaborate with multi-functional engineering teams to document r

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today, SpaceX is actively developing the technologies to make this possible, with the ultimate goal of making life multiplanetary and expanding consciousness to the stars. SpaceXSI is building Super Intelligence to help humanity understand the universe. Our teams are building the full Super Intelligence stack: from our Colossus supercomputers, to Grok models, to our suite of applications, including Grok Bot, Grok Build, Grok Imagine, Grok Voice, and X. We're creating a powerful flywheel where more compute trains better models, better models power more useful products, and what we learn from people using those products shapes what we build next. ABOUT THE ROLE: As a member of the Supercomputer Physical Infrastructure team, you will provide hands-on support for the integration, commissioning, troubleshooting, and maintenance of control systems across our AI training campuses. This role focuses on safe, structured execution of repairs and recoveries that maximize uptime; wiring and building industrial control panels; supporting PLC, HMI, and SCADA systems; and keeping cooling plants, electrical distribution, liquid-cooling loops, and data halls running. You will work closely with Controls Engineers on the same team. This position is based in Memphis, TN, with work across the Memphis / Southaven campus. RESPONSIBILITIES: Support integration and commissioning of vendor and OEM equipment into campus BMS, EPMS, and SCADA systems and plant PLC controls Perform safe controls and electrical work within LOTO, arc-flash, interlock, bypass-control, and restart-verification requirements; identify hazards, verify zero energy, validate safety devices after repair, and escalate unsafe conditions or unauthorized changes Maximize uptime of cooling, electrical, and facility control assets through hands-on troubleshooting, basic repairs, a

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today, SpaceX is actively developing the technologies to make this possible, with the ultimate goal of making life multiplanetary and expanding consciousness to the stars. SpaceXSI is building Super Intelligence to help humanity understand the universe. Our teams are building the full Super Intelligence stack: from our Colossus supercomputers, to Grok models, to our suite of applications, including Grok Bot, Grok Build, Grok Imagine, Grok Voice, and X. We're creating a powerful flywheel where more compute trains better models, better models power more useful products, and what we learn from people using those products shapes what we build next. ABOUT THE ROLE: SpaceXSI is looking for a highly skilled and versatile OT (Operational Technology) Systems Engineer to implement and support the backend infrastructure for our next-generation controls and industrial software platforms for our physical infrastructure. This role is embedded within the mission IT organization to provide support to dedicated controls engineering organizations while leveraging adjacent IT expertise, tooling, and technologies. This role will balance support of legacy controls support systems with modernization and continuous improvement initiatives. The ideal candidate thrives in high stakes settings, brings a strong sense of urgency balanced with operational excellence, and combines deep OT expertise with IT technologies such as virtualization, VDI, GitOps, network level redundancy and edge compute solutions to create streamlined and secure ICS environments. RESPONSIBILITIES: Design, deploy, and augment next-generation OT environments that support plant and launch systems across multiple sites. Install, configure, maintain, and support industry standard controls software platforms as well as internally developed HMIs. Integrate established and emerge

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today, SpaceX is actively developing the technologies to make this possible, with the ultimate goal of making life multiplanetary and expanding consciousness to the stars. SpaceXSI is building Super Intelligence to help humanity understand the universe. Our teams are building the full Super Intelligence stack: from our Colossus supercomputers, to Grok models, to our suite of applications, including Grok Bot, Grok Build, Grok Imagine, Grok Voice, and X. We're creating a powerful flywheel where more compute trains better models, better models power more useful products, and what we learn from people using those products shapes what we build next. ABOUT THE ROLE: SpaceXSI is looking for an exceptional network engineer with experience in mission-critical or large-scale production environments to support our supercomputer infrastructure. As a member of the Physical Infrastructure Networking team, you will provide operational and designs services for physical infrastructure networks. The ideal candidate thrives in intense, high flux environments, brings a strong sense of urgency balanced with operational excellence, communicates effectively, and demonstrates high levels of technical acumen. RESPONSIBILITIES: Design and implement highly available networks, carefully balancing various routing and redundancy technologies depending on unique requirements between production and launch. Design and maintain mission data center and site networks in accordance with company network standards. Collaborating with adjacent infrastructure and enterprise teams. Evaluate, procure, and deploy network hardware including switches, firewalls, multiplexing and SDWAN appliances. Contribute to ever maturing network automation tooling; implementing configuration analysis, linting, and scalability into the deployment framework. Plan and coordinate n

Senior Scientist – Physical AI for Surgical Robotics (Cambridge, MA) — Cambridge (US), Massachusetts, United States. Apply via Workday.

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. We are hiring a Staff Research Scientist, Physical AI for our AI Research team . You will build the next-generation training and learning platform for physical AI: models that perceive, reason about, and act within structured environments . This is a greenfield (0 to 1) effort at the intersection of representation learning, world models, and policy optimization. You will help define its technical direction from day one. AS A STAFF RESEARCH SCIENTIST YOU WILL: Design and build scalable training infrastructure for representation models (e.g., contrastive and self-supervised approaches like CLIP/SigLIP, DINO/MAE, and joint-embedding predictive architectures) Develop latent world models that learn environment dynamics through imagined rollouts, enabling model-based reasoning and planning (Dreamer-style, I-JEPA/V-JEPA families) Architect and implement action/policy model pipelines, including vision-language-action models and diffusion-based policy learning Build generative simulator frameworks that produce controllable, physically plausible future states (video world models in the spirit of Cosmos/Genie/Sora) Develop multimodal generative model capabilities that fuse visual, language, and structured inputs for downstream reasoning and decision-making Lead cross-team technical de

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products! We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions! In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will own physical implementation and top-level integration of large digital designs in our NAND products. Drive blocks and full-chip partitions through synthesis handoff, floorplan, place-and-route, and timing/DRC/LVS closure. Perform hierarchical design planning and top-level assembly. Responsibilities will include, but are not limited to: Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions Leading all aspects of and managing the layout process including floor-planning, placement, and routing

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today, SpaceX is actively developing the technologies to make this possible, with the ultimate goal of making life multiplanetary and expanding consciousness to the stars. SpaceXSI is building Super Intelligence to help humanity understand the universe. Our teams are building the full Super Intelligence stack: from our Colossus supercomputers, to Grok models, to our suite of applications, including Grok Bot, Grok Build, Grok Imagine, Grok Voice, and X. We're creating a powerful flywheel where more compute trains better models, better models power more useful products, and what we learn from people using those products shapes what we build next. ABOUT THE ROLE: As a member of the facility operations team, you will apply your knowledge, experience, and creativity to help design, build, and activate some of the world’s most technically advanced data center facilities. Process flow, project planning, and detailed department-level metrics and dashboards all fall under the scope of this role. If you like strategic planning, juggling many different priorities, improving processes, and spending your time in a dynamic work environment, then this team may be for you! RESPONSIBILITIES: Develop internal visual standards for internal work boards, JIRA queuing, PowerBI dashboards, and department workflow Maintenance program enhancement – increase attention on poor-health hardware and descope unnecessary work Support department continuous improvement projects such as new process rollouts/standardization Integrate with all levels of the business to understand current workflows and identify systematic gaps Define and develop department-level metrics & associated dashboards that quantify the health of our operations and influence change Conduct in-depth analyses through SQL queries and other data analysis methods to dive into

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. The Role We are seeking a thorough SOC Physical Verification & Integration Specialist to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks. You will act as the critical bridge between block-level implementation, top-level integration, and final foundry signoff, ensuring that complex physical bottlenecks are resolved without compromising power, performance, or area (PPA). Key Responsibilities Top-Level Physical Integration: Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs). Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration. Hierarchical Verification Methodology: Architect and deploy highly efficient, hierarchical physical verification (PV) flows. Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs. Signoff Execution & Debugging: Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry-standard tools (e.g., Siemens Calibre) at advanced process nodes (5nm, 3nm, or below). Cross-Functional Collaboration: Partner tightly with the Physical Design (PD