Signal Integrity Hardware Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Principal Layout Designer in the Next-generation HBM Architecture Team , you will drive layout for 3D-stacked, high-performance memories. Apply your knowledge to deliver high-quality layout designs across analog and/or mixed-signal domains in collaboration with peer architecture, design, and packaging teams. Implement layout designs for early architecture concepts to demonstrate feasibility and identify optimizations. Responsibilities: Design layouts for critical analog and mixed-signal blocks. Drive exploratory layout process for next-generation architectures, including floorplanning, placement, and routing. Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation. Collaborate and communicate across domains, including signal integrity, architecture, design, and advanced packaging, to ensure successful architecture exploration. Minimum Qualifications: Hands-on layout experience with critical analog blocks and full designs. Experience with Cadence VLE/VXL and Mentor Graphics Calibre DR

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary This position supports Micron’s DRAM Tester Solutions group, focusing on physical design implementation for processors, controller architectures, and ASICs. The role is responsible for full‑chip and block‑level physical design closure, low‑power implementation, timing, power, and signal integrity signoff, and successful tape‑out across advanced technology nodes. Responsibilities: Lead block‑level and full‑chip physical design including floorplanning, placement, CTS, routing, and tape‑out. Drive timing closure across multiple modes and corners using industry‑standard STA tools. Perform power integrity, IR/EM, and power grid closure to meet signoff requirements. Develop and optimize APR flows, scripts, and methodologies for PPA improvements. Own subsystem or full-chip closure work while coordinating with cross-functional teams. Minimum Qualifications: Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering, Electronics, or Computer Architecture. Minimum of 15 years of hands‑on ASIC physical design implementation experience. Proven experience with multiple production tape‑outs in advanced process nodes. Strong expertise in low‑power design techniques including UPF/CPF and multi‑voltage systems. Proficiency in scripting languages such as Tcl, Perl, or Python for flow automation. Preferred Qualifications: Experience with Synopsys and Cadence physical design and ti

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Lead Principal Engineer, Layout Design at Micron, you will be at the forefront of developing groundbreaking memory solutions! This role is an outstanding opportunity to lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts. You will collaborate with a world-class team of Circuit Designers, Verification Engineers, CAD/Methodology experts, Process Integrators, Product Engineers, Test/Probe specialists, Assembly professionals, and Marketing strategists. Together, we will drive cost, quality, reliability, time-to-market, and customer happiness through outstanding layout and build. Key Responsibilities Lead the layout build and physical realization of new memory products. Interpret device and circuit specifications to implement custom layout solutions meeting PPA (power, performance, area) and reliability targets. Develop hierarchical layouts for analog, digital, and memory-array-related circuitry using industry-standard EDA tools. Build block and top-level floorplans optimizing placement, routing resources, signal integrity, power delivery, and manufacturability. Optimize layout for critical metrics such as die size/area efficiency, matching, coupling/noise, and timing. Produce layout collateral and documentation for cross-team integration. Physical Verification and Tapeout Signoff Run and debug physical verification flows and ensure closure using indust

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron is seeking a Principal Physical Design Engineer to provide technical leadership for advanced DRAM digital design implementation and signoff methodologies. This role will drive physical design execution from RTL through tapeout, with a strong focus on timing closure, power integrity, EMIR analysis, and design reliability. The engineer will collaborate across architecture, RTL, implementation, CAD, and technology teams to develop scalable physical design solutions that achieve power, performance, area (PPA), and reliability targets for next-generation memory products. Additionally, this individual will lead methodology innovation, mentor engineers, and influence the future roadmap for physical design and power integrity across the organization. Responsibilities Lead physical design implementation of complex DRAM digital designs, including floorplanning, place and route, clock tree synthesis, timing closure, and tapeout activities. Drive power integrity strategies and signoff methodologies, including PDN planning, IR drop analysis, electromigration (EM) verification, and EMIR signoff. Collaborate with multi-functional teams to resolve timing, congestion, power, signal integrity, and reliability challenges at both block and full-chip levels. Develop and deploy methodology improvements, automation solutions, and guidelines to improve build quality, efficiency, and scalability. Mentor engineers and provide technical leadership while influencing future memory products t

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to seek, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. What you’ll be doing: Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value-conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive, Professional, Data Center, Deep Learning, and AI), all using Cadence PCB design tools. Focus will be on the complete development of CAD layout from symbol creation, floor planning, and detailed component placement, constraints management, with a concept of topology and signal/trace integrity. You will be responsible for the design releases required generation of artwork files, ODB++, and electronic PCB documentation. Your designs will need to follow SI constraints, EMI/RFI control and FCC, UL and European regulations, IPC specifications and NRC regulations. What we need to see: B.Sc. in Electronic Engineer degree or equivalent experience. 5+ years of experience in high-speed design. Having a detailed knowledge of circuit design and consideration for layout, routing, and timing constraints, DFM, DFA, DFT constraints in volume manufacturing is needed for this role. Be an authority in using Cadence Allegro PCB design tools. Have a deep understanding of High-Density Interconnect PCB layout and PCB Signal Integrity. Knowledge in PCB ma

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Craft and analyze digital and analog circuits used in the development of memory products including simulating, optimizing, and floor planning DRAM circuits. Collaborate with various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to proactively craft HBM products that optimize all manufacturing functions and assure the best performance, power, cost, quality, reliability, time-to-market, and customer happiness. Innovate and integrate end-toend groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). Employer will accept a Master’s degree in Electrical Engineering, Physics, Computer Engineering, Semiconductor Engineering or a related field and 10 years of experience in the job offered or in a related field. Position requires: 1. High-speed memory design on data paths, from I/O interface to core array 2. 2. Power domain network analysis 3. Memory test architectures like MBIST and production silicon validation 4. Digital design methodologies experience including RTL design, synthesis, and physical implementation 5. ASIC design development using digital design 6. Memory core timing, latency control, and signal integrity consideration in advanced designs <p style="

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Development Engineer in the Media Health team, you will connect various engineering groups and specialties. You will combine diverse expertise to develop new and improved test strategies, features, and technologies. This role offers an outstanding opportunity to work with the newest technology, helping to build the future of memory and storage solutions. You will have or develop guide capability with Probe, and/or ATE test code and testing techniques used to validate and ensure device performance. You will assist in debugging code and aiding other specialists in the characterization of applicable HBM devices. In this role, your additional responsibilities include an in-depth understanding of general device functionality specific to HBM products as well as schematics and signal integrity. Responsibilities: Collaborate with Design Engineering (DE) to conduct pre-silicon simulations to validate test strategies and circuits for Test. Provide feedback to DE, Test Engineering (TE), and others in Product Engineering (PE). Support pre-silicon checklist tasks and collaborate with TE to identify vital tester resources. Collaborate with TE and PE to adjust test programs for particular product needs to guarantee that silicon performance aligns with expectations. Support TE by aiding in test program debug, data analysis, and test development using AI assistants. Assist fabrication sites and process integration with test creation to improve effective process feedback. Debug and i

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Engineer in the High Bandwidth Memory (HBM) Media Health (MH) team, you will work with Fab, Yield Improvement, Design, and other engineering groups passionately focused on HBM. You will develop, deploy, optimize, and innovate test strategies for Micron's DRAM in HBM products. The team acts as a key partner of these engineering groups and specialties, focusing on innovating new and improved test strategies and features. You will guide development for Probe (wafer level test), Burn-in, and ATE test code and testing techniques used to validate and ensure device performance. You will assist in debugging code and aiding other specialists in the characterization of applicable HBM devices. In this role, your additional responsibilities include an in-depth understanding of general device functionality specific to HBM products as well as schematics and signal integrity. Responsibilities: Work with Design Engineering to run simulations pre-silicon to validate DFT circuits and test modes as well as communicate design issues found. Work on pre-silicon tasks with MH and test teams to define required tester resources. Work with Test Engineering and HBM Product Engineering to ensure specific product requirements or limitations are comprehended, leading to silicon performance matching expectations. This work includes test program debug, examination of data, and test development. Support the ID1 fabrication site Process Integration and Yield Enhancement through test development, DOE data analysi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Engineer in the High Bandwidth Memory (HBM) Media Health (MH) team, you will work with Fab, Yield Improvement, Design, and other engineering groups passionately focused on HBM. You will develop, deploy, optimize, and innovate test strategies for Micron's DRAM in HBM products. The team acts as a key partner of these engineering groups and specialties, focusing on innovating new and improved test strategies and features. You will guide development for Probe (wafer level test), Burn-in, and ATE test code and testing techniques used to validate and ensure device performance. You will assist in debugging code and aiding other specialists in the characterization of applicable HBM devices. In this role, your additional responsibilities include an in-depth understanding of general device functionality specific to HBM products as well as schematics and signal integrity. Responsibilities: Work with Design Engineering to run simulations pre-silicon to validate DFT circuits and test modes as well as communicate design issues found. Work on pre-silicon tasks with MH and test teams to define required tester resources. Work with Test Engineering and HBM Product Engineering to ensure specific product requirements or limitations are comprehended, leading to silicon performance matching expectations. This work includes test program debug, examination of data, and test development. Support the ID1 fabrication site Process Integration and Yield Enhancement through test development, DOE data analysi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of the Heterogeneous Integration Group within Technology and Products, where we build High Bandwidth Memory solutions that power AI and ML platforms. Our team works at the edge of what’s possible, stacking and integrating advanced silicon technologies to deliver industry‑leading bandwidth, density, and power efficiency. We move fast, solve hard problems, and set technical direction others follow! This role sits at the center of next‑generation HBM development. As a senior SI/PI technical authority, you will shape system‑level decisions that directly impact performance, reliability, and scalability across multiple product generations. If you enjoy deep technical ownership, complex problem solving, and influencing architecture from concept to sign‑off, this role offers both challenge and impact. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Lead signal integrity channel analysis for 2.5D and 3D silicon interposers, including frequency‑ and time‑domain evaluation Define and drive power delivery architecture, impedance targets, and transient analysis Perform electromagnetic extraction and modeling across PCB, package, and interposer designs Establish SI/PI standards, methodologies, and sign‑off criteria for HBM system designs Provide clear technical direction in ambiguous or incomplete design environments Minimum Qualifications: 7 years of experience in

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building innovative physical design capabilities that help bring advanced semiconductor products from concept to silicon. Our team collaborates across design, verification, and manufacturing disciplines to deliver high-quality solutions using leading-edge technologies. We value technical excellence, continuous learning, and a culture of teamwork and innovation. As a Physical Design Engineer, you will play a key role in driving semicustom physical implementation from netlist handoff through tapeout. You will work closely with cross-functional engineering teams to optimize design quality, achieve physical signoff, and support successful product delivery in advanced technology nodes. Responsibilities: Execute the semi-custom physical design flow from netlist handoff through physical verification and tapeout Develop and maintain floorplans, placement, routing, power distribution networks (PDN), and physical design constraints Perform DRC, LVS, parasitic extraction, and physical signoff activities Analyze and resolve timing, signal integrity, electromigration, IR drop, reliability, and manufacturability issues Partner with cross-functional teams to drive design closure, debug issues, and support tapeout readiness Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field Experience in VLSI physical design, semiconductor lay

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for design of large form factor IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Design of IC substrates using Siemens Xpedition IC package design software - Work closely with stakeholders to meet design requirements - e.g., receive feedback from silicon testchip, signal integrity (SI), power integrity (PI), thermal simulation, and system integration engineers - Deliver and disseminate design milestones to stakeholders - Design validation and verification; including DRC and LVS - Advanced packaging design integration (2.5D and 3D) with IC substrate - Tapeout of designs with substrate suppliers in collaboration with Intel substrate teams - Communicate designs in presentations and relevant documentation - Stay curre

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Interposer Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for physical design and integration of advanced packaging interposers within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Physical design and integration of interposers used within advanced packaging for quantum computing - Work closely with stakeholders to meet design requirements - e.g., receive feedback from silicon testchip, signal integrity (SI), power integrity (PI), thermal simulation, and system integration engineers - Design validation and verification; including DRC and LVS - Deliver and disseminate design milestones to stakeholders - Communicate designs in presentations and relevant documentation - Stay current with the latest developments in packaging technology and design techniques by attending conferences and reading papers As

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building innovative physical design capabilities that help bring advanced semiconductor products from concept to silicon. Our team collaborates across design, verification, and manufacturing disciplines to deliver high-quality solutions using leading-edge technologies. We value technical excellence, continuous learning, and a culture of teamwork and innovation. As a Physical Design Engineer, you will play a key role in driving semicustom physical implementation from netlist handoff through tapeout. You will work closely with cross-functional engineering teams to optimize design quality, achieve physical signoff, and support successful product delivery in advanced technology nodes. Responsibilities: Execute the semi-custom physical design flow from netlist handoff through physical verification and tapeout Develop and maintain floorplans, placement, routing, power distribution networks (PDN), and physical design constraints Perform DRC, LVS, parasitic extraction, and physical signoff activities Analyze and resolve timing, signal integrity, electromigration, IR drop, reliability, and manufacturability issues Partner with cross-functional teams to drive design closure, debug issues, and support tapeout readiness Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field Experience in VLSI physical design, semiconductor lay

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an Electrical Design Engineer in the Systems Integration Group (SIG) of Micron Technology, Inc, you will design load boards that support semiconductor memory manufacturing, as well as resolve issues with and develop improvements to deployed automated test equipment (ATE) products. Load boards, used for testing memory devices after they are manufactured & packaged, are the contact interface between ATE and pins of the device under test (DUT). Load boards contain the necessary components to: setup the DUT for correct testing by the ATE; route power, test, and response signals between the DUT and the ATE; provide additional test capabilities that the ATE may not be able to provide; and, alternately, testing or calibrate the ATE itself. Load board design considerations, like other PCB assemblies, include DC power supply distribution, clock & digital routing, and high-speed signal integrity. You will apply circuit theory to design load board solutions working closely with other team members located around the world that include other engineering disciplines, technicians, procurement, planning, and external contract manufacturers. Responsibilities and Tasks Develop requirements specifications Analog and digital circuit design and simulation Schematic capture Work closely with layout designers to develop PCBs Author test plans and lab repo