Signal Integrity Hardware Engineer Jobs

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Join the Pipeline Engineering team at Everpure™ as a Full Stack Software Engineer to build and scale the pipeline visibility layer for FlashArray, FlashBlade, and Hyperscale — the core platform through which engineers and customers understand and act on CI results . In this high-impact position, you will own responsive web interfaces, API gateway architecture, and AI-assisted workflows that convert raw pipeline data into actionable signal, eliminating operational toil across our engineering organization. WHAT YOU'LL DO Build the Pipeline Visibility Layer: Architect and ship high-performance web applications using modern JavaScript/TypeScript frameworks to deliver real-time pipeline status, test results, and failure analytics at enterprise scale. Own Gateway & Backend Services: Develop and operate low-latency API gateways and backend microservices using typed systems languages (such as Go or Rust) to aggregate data across systems, enforce strict multi-tenant boundaries, and maintain reliable system contracts. Deliver Secure Access Controls: Implement robust authentication and authorization protocols (OAuth2/OIDC, SSO, RBAC) to ensure internal teams and external customers experience seamlessly scoped and fully audited access. Integrate AI Triage Workflows: Engineer retrieval-augmented generation (RAG) pipelines and LLM integrations over test metadata and failure logs to automate root-cause summaries, flak

About Hark Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory. We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world. To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems. About the Team You'll build the product surfaces of Hark — the interfaces and experiences users interact with every day across voice, text, and vision. That means translating what our agent can do into something that feels fast, intuitive, and trustworthy. The gap between a capable AI and one people actually want to use is a product problem, and this role owns it. This is a high-ownership role on a small team. You'll work directly with designers and model researchers, and what you ship will define how people experience Hark. Responsibilities Design and build the product surfaces of Hark. The interfaces, conversations, and agentic experiences that users interact with every day across voice, text, and vision. Work closely with designers to ship interactions that feel fast, reliable, and genuinely useful. The details matter here. Own features end-to-end, from early prototyping to production deployment and iteration based on real usage. Build the frontend for agent workflows that integrate tool use, memory retrieval, and multi-step reasoning. Making model capabilities feel coherent and trustworthy to the person using them. Instrument and evaluate what you ship. Track quality, gather signal, and improve. Requirements Strong frontend engineering fundamentals.

About the Team The Hardware Health and Observability team owns the end-to-end health lifecycle of OpenAI’s global compute fleet. Our mission is to maximize healthy, usable compute across accelerator vendors, generations, cloud providers, and regions through reliable health signals, automated remediation, and scalable operational tooling. We build the systems that observe, detect, remediate, and verify hardware issues across GPUs, CPUs, networking, and platform infrastructure, enabling frontier model training and inference workloads to run reliably at hyperscale. We are the last line of defense for the success of OAI’s production and research workloads. About the Role On the Hardware Health and Observability team, you’ll build critical infrastructure that keeps OpenAI’s largest compute clusters healthy and operational at scale. Even small numbers of unhealthy systems can impact large-scale training and inference workloads. This team focuses on minimizing downtime, improving fleet efficiency, and ensuring compute resources remain continuously available to researchers and product teams. Engineers on this team own problems end-to-end, from defining health signals and debugging failures to building automated remediation systems that operate across millions of GPUs globally. In this role, you will: Define and maintain health signals across GPUs, CPUs, networking, and platform infrastructure. Build and evolve health checks that detect, remediate, and verify failures at scale. Ensure critical health checks execute with minimal latency to maximize workload uptime. Investigate hardware failures and system-level issues across large-scale compute environments. Own node lifecycle workflows including drain, quarantine, repair, RMA, and return-to-service processes. Build automation and tooling that enables global cluster management with minimal manual intervention. Partner with workload, reliability, and provider teams to integrate health signals into training and inference system

About the Team The Future of Computing Research team is an applied research team within OpenAI’s Consumer Devices group. We study how AI systems perceive people and their surroundings, and we turn that research into capabilities for future products. Our work spans machine learning, sensing, and hardware, with a focus on building systems that work beyond controlled environments. About the Role We’re looking for a machine learning engineer to help shape how future AI systems understand the physical world and the people in it. The role focuses on multimodal perception and authentication, bringing together signals from cameras, microphones, and other sensors. You’ll work with specialized perception models and larger multimodal models, and partner with hardware, firmware, software, and product teams to bring new research into real-world systems. This role is based in San Francisco. We work in the office three days per week and offer relocation assistance. In this role, you will: Research and develop multimodal perception and authentication methods across visual, audio, and other sensing signals. Explore how specialized perception models and larger multimodal models can work together. Design data, training, and evaluation approaches that improve performance in real-world conditions. Study model behavior, robustness, and failure modes across sensing, data, and deployment environments. Integrate and validate new capabilities in real-time or resource-constrained systems. Work with hardware, firmware, software, and product teams to turn research into working systems. You might thrive in this role if you: Have a strong background in computer vision, audio or speech machine learning, multimodal learning, or sensing. Have experience developing specialized machine learning models, larger multimodal models, or both. Have brought research ideas into practical systems, prototypes, or products. Know how to design experiments, build evaluations, and investigate model behavior. Have wo

About the Team The Systems Integration team is responsible for building the infrastructure, tooling, and validation systems that ensure our device software is reliable, testable, and ready to ship. We design and maintain automated test frameworks, hardware-in-the-loop labs, and release pipelines that keep quality signals trustworthy and enable rapid, safe product launches. Our work spans developer tools, automation, systems integration, and cross-team collaboration to ensure every release meets the highest standards. About the Role As a Software Engineer, Quality and Developer Tools , you will build and own the systems that validate our device software—from test frameworks and regression infrastructure to hardware-in-the-loop labs and release gates. You’ll design the tooling and automation that keep quality signals trustworthy, integrate them into CI/CD, and make it easy for engineers and QA vendor technicians to execute reliable, repeatable workflows. We’re looking for engineers with deep experience in software quality, automation, developer tooling, and hardware-software integration who thrive on building scalable, reliable systems for validation and release readiness. This role is based in San Francisco, CA. We use a hybrid work model of four days in the office per week and offer relocation assistance to new employees. In this role, you will: Test infrastructure & frameworks: Design, implement, and maintain a unified test framework for device software across unit, integration, system, and end-to-end testing, with reproducible runs and integrations with GitHub, Linear, and Slack. CI/CD integration & releases: Integrate test suites with Buildkite, enforce promotion criteria for staging and production, auto-file regressions, and publish traceable artifacts and release notes. Hardware-in-the-loop lab design & orchestration: Plan and bring up racks, power and networking systems, and orchestration for device testing; support automated flashing, provisioning

Sr Software Engineer - Distributed Systems Engineer, EDA Infrastructure NVIDIA is hiring engineers to build and scale the infrastructure that supports our Electronic Design Automation (EDA) workloads. We are looking for engineers with strong programming skills, a deep understanding of distributed systems, experience operating large-scale production infrastructure, and excellent communication and planning abilities. You will help design reliable automation and platform services that manage large fleets of GPU-based and CPU-based compute systems used by engineering teams across NVIDIA. The ideal candidate is comfortable working across software, operating systems, cluster schedulers, networking, storage, and physical hardware. You should enjoy solving complex operational problems, eliminating repetitive work through automation, and building systems that remain reliable as infrastructure grows. If you are creative, pragmatic, and motivated to improve how critical engineering workloads are delivered, we would like to hear from you. What You Will Be Doing: Design and build platforms that automate the provisioning, configuration, operation, and lifecycle management of large-scale GPU and CPU compute infrastructure. Develop monitoring, health-management, and remediation systems that improve the reliability, availability, and utilization of EDA compute environments. Automate hardware deployment, operating-system configuration, firmware and software updates, cluster enrollment, and recovery workflows. Build reliable services and workflows that integrate with workload schedulers, infrastructure management systems, and observability platforms. Use hardware diagnostics, operating-system signals, scheduler data, and network and storage telemetry to identify

Why Sony Interactive Entertainment? Sony Interactive Entertainment isn’t just the Best Place to Play — it’s also the Best Place to Work. Sony Interactive Entertainment (SIE) is the company behind the PlayStation brand. As a subsidiary of Sony Group Corporation, we’re part of a proud legacy of innovation and excellence. SIE is a dynamic technology company, delivering cutting-edge hardware and network services to more than 100 million people and an entertainment leader, home to some of the most beloved and recognizable intellectual properties (IP) in the world. Our role at SIE is to create and nurture the experiences under the PlayStation brand, a name synonymous with entertainment excellence and creativity. Department overview: The Senior Solutions Engineer leads the design and delivery of complex employee technology automations and integrations. The role converts agreed architecture and service needs into reliable production solutions that help teams detect issues earlier, resolve appropriate cases safely, and spend more time on high value employee enablement. This individual owns substantial engineering work from technical design through testing, deployment, monitoring, and operational handover. What you’ll be doing: Solution delivery Lead technical design and implementation for defined complex automation or integration initiatives within agreed architecture and security standards. Build and integrate APIs, workflows, scripts, and platform capabilities across employee technology and support systems. Use endpoint and service signals to support detection, validation, approved remediation, exception handling, and outcome recording. Plan and execute testing, deployment, monitoring, rollback, documentation, and operational handover. Platform engineering and integration Design and implement robust integrations across relevant services such as ServiceNow, Moveworks, Jira, Slack, Nexthink, Jamf , Microsoft Intune, Microsoft

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities: Develop Linux user-space firmware for Ubiquiti networking products; Collaborate with global firmware, hardware, cloud, and product teams throughout the product lifecycle; Design, implement, and maintain system services, management daemons, libraries, and product business logic; Develop network-facing applications using sockets, IPC mechanisms, netlink, and event-driven I/O; Integrate open-source packages and third-party components into our OpenWrt-based firmware and build systems; Maintain and improve existing firmware, focusing on stability, performance, security, and resource efficiency; Develop interfaces between low-level platform components, device-management services, and higher-level product features; Diagnose complex laboratory and field issues using logs, packet captures, tracing, core dumps, and profiling tools. Requirements: 3+ years of embedded Linux software development experience using C or C++; Strong understanding of Linux internals, including processes, threads, memory management, filesystems, signals, and service lifecycle; Experience with Linux networking, sockets, IPC, netlink, epoll, and asynchronous application design; Solid networking fundamentals, including Ethernet, TCP/UDP, IPv4/IPv6, routing, bridging, firewalls, and DNS/DHCP.; Experience with Git, Bash, cross-compilation, toolchains,

Job Details: Job Description: We are seeking an experienced Analog Design and Infrastructure DA Manager to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs..The ideal candidate combines deep analog/mixed-signal design flow and e-test structure development expertise with strong infrastructure leadership and disciplined configuration/data management practices. Key Responsibilities-1. Analog Design Environment and Flow Management-Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso ,Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC).Support simulation environments including HSPICE, Corner analysis.Drive automation and methodology improvements to reduce turnaround time and increase design robustness. 2. Infrastructure and Compute Management Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM). Manage LSF/grid environments and job scheduling systems. Ensure scalability, system monitoring, high availability, and performance optimization. Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery. Maintain secure, access-controlled design environments aligned with IP protection policies. 3. Design Data, Manifest and Configuration Management Design Data Governance Manage large-scale analog design libraries, hierarchical database structures, and technology libraries. Define backup, archival, and retention policies for tapeout-critical data. Implement data integrity validation and corruption prevention controls. Oversee distributed stor

About the Team OpenAI’s acquisition of io marks our entry into consumer hardware and our ambition to define the next human–computer interface. Success in hardware requires strong financial stewardship across the full product cost stack—from early design and sourcing decisions through manufacturing, logistics, inventory, returns, and warranty. Hardware Finance works across Product, Supply Chain, Operations, Accounting, Systems/Data, and Finance to connect business decisions to product cost, inventory, cash, COGS, and margin. About the Role We are seeking a Hardware Finance Manager to own an assigned area of hardware COGS and inventory end to end. The initial assignment will depend on business priorities and the successful candidate’s expertise. It may include BOM and product cost, manufacturing variance analysis, inventory planning, logistics, returns and warranty, customer support, or another connected set of hardware-finance responsibilities. This is an individual-contributor role with broad scope. Prior hardware experience and deep, hands-on expertise in at least two relevant domains are required. The person will be expected to operate independently, build reusable processes and analytical workflows, and remain accountable for the analysis, judgment, and recommendations. In this role, you will: Own an assigned area of hardware COGS and inventory end to end. Own forecasting, close, and business variance analysis for the assigned scope. Provide hardware leadership with clear variance explanations, trend analysis, and forward-looking signals that connect business and supplier decisions to inventory, cash, COGS, and margin. Partner with business teams and Finance Platforms to establish the financial data, systems, and dashboards needed to support analysis. Ensure data integrity and governance through clear definitions, ownership, validation checks, controls, and review processes. Improve forecasting, reporting, systems, and finance processes so they remain reliable an

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As the SAP Plan-to-Forecast Lead, you will serve as the functional business owner driving Everpure’s global demand forecasting and Sales and Operations Planning (S&OP) capabilities. Operating at an individual contributor level, you will bridge market intelligence, commercial strategies, and operational execution on the Everpure Platform. By determining optimal forecasting methods and evaluating complex, variable demand factors across global business units, you will align Sales, Finance, Marketing, and Supply Planning teams around a single, highly accurate consensus demand plan. WHAT YOU'LL DO Drive Consensus S&OP & Demand Planning: Determine methods, processes, and execution criteria for the monthly S&OP demand review cycle—facilitating unconstrained demand plan preparation, commercial input consolidation, and executive consensus reviews. Architect SAP IBP Forecasting Frameworks: Define and optimize the statistical forecasting framework within SAP IBP Demand Planning, selecting statistical models, establishing error measurement standards (MAPE, WMAPE, bias), and leading exception-based review strategies. Integrate Cross-Functional Market Signals: Coordinate across Sales, Marketing, Product, and Finance teams to incorporate new product introductions, promotional events, phase-outs, and revenue targets into baseline demand forecasts. Govern Demand Master Data & KPIs: Own the business definition a

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the Compute and Memory Business Unit (CMBU), driving the innovation behind Micron's next generation DRAM solutions for AI, data center, and client computing platforms. Our team collaborates across product architecture, design, validation, and system engineering to solve complex challenges in bandwidth, power, reliability, and scalability. Together, we help shape the future of memory technology for the world's most demanding compute environments. As a Product Architecture Engineer focused on Signal Integrity (SI) and Power Integrity (PI), you will define the electrical architecture that enables next-generation DRAM products. This highly visible role combines deep technical expertise with system-level thinking to influence product roadmaps, guide design decisions, and partner with industry-leading ecosystem stakeholders. Your work will help deliver memory solutions that power tomorrow's AI and high-performance computing platforms. Responsibilities: Lead SI/PI architecture pathfinding for next-generation DRAM products across AI, data center, and client platforms Define channel, package, board, and module-level SI/PI requirements and design targets for product development Evaluate DDR and LPDDR electrical performance, including timing, jitter, signal margin, crosstalk, impedance, reflections, and power delivery behavior Develop and apply modeling, simulation, and correlation methodologies using industry-standard EDA tools and validation data Partner across design, validation, package,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a Signal Integrity Engineer to join our growing team. The ideal candidate will have a wealth of exposure designing high speed interconnects, breakout design, material trade-offs and verification. A background in electrical engineering, electronics or relevant fields is required. Must love all things high speed! This role is hybrid, based out of Santa Clara, CA or Austin, TX or Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a Bachelor’s degree in Electrical Engineering (or equivalent) and 5+ years working in high-speed digital design with a focus in high-speed PCB or package design at 10Gbps and above (e.g. 100GbE, GDDR6, PCIe Gen5+). You’re comfortable working with high-speed performance metrics such as ICR, ERL, COM, NEXT, and FEXT as well as knowledge of high-speed connector technologies, including NPO, CPO, and emerging standards. You are proficient with PCB ECAD tools (ideally Cadence Allegro). You communicate clearly (written and verbal), think critically, and love solving complex signal integrity problems. You’re enthusiastic about all things high speed and enjoy collaborating acro

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Signal Integrity (SI) Research & Development team enables the electrical performance of Micron's industry-leading memory and storage products, including DRAM, LPDRAM, NAND, HBM, SSDs, and emerging memory technologies. The team works across silicon, package, PCB, and system-level designs to develop high-speed signaling and power delivery solutions that support next-generation computing, AI, networking, automotive, mobile, and data center applications. As a Signal Integrity Engineer, you will support the design, analysis, and validation of high-speed memory interfaces and power distribution networks across Micron's product portfolio. Working alongside experienced engineers, you will use modeling, simulation, measurements, and AI-enabled workflows to evaluate signal and power integrity performance, support product development, and contribute to future technology and industry standards initiatives. Responsibilities Support signal integrity and power integrity analysis for high-speed memory interfaces and power distribution networks through modeling, simulation, measurement, and correlation activities. Collaborate with silicon, package, product, validation, and system engineering teams to ensure product electrical performance across all stages of development. Develop and evaluate die, package, PCB, and system-level models to identify performance risks and optimization opportunities. Apply AI-enabled tools and agentic workflows to improve engineering efficiency, automate analysis, improve

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Principal Signal Integrity Engineer — Interface Pathfinding About the Role At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team operates at the leading edge of that mission — serving as a bridge between corporate strategy and engineering through forward-looking investigation and development of energy-efficient bandwidth solutions. Our work spans innovative circuit, signaling, packaging, and interconnect solutions with a 3–5 year technology horizon, grounded in rigorous analysis, hands-on measurement, and a commitment to building a robust intellectual property portfolio. As a Principal Signal Integrity Engineer , you will be a core technical contributor on a deliberately small, senior team united around the goal of preparing high-speed interface innovations for high-confidence product adoption. What You’ll Work On Micron’s Interface Pathfinding team investigates and validates novel interconnect and signaling solutions for high-speed memory and die-to-die interfaces. The signal integrity scope is broad and analytically deep — spanning electrical modeling, channel analysis, and substrate evaluation — with an emphasis on original analysis rather than execution of established playbooks. Key signal integrity domains include: Intercon