Signal Integrity Hardware Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Principal Signal Integrity Engineer — Interface Pathfinding About the Role At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team operates at the leading edge of that mission — serving as a bridge between corporate strategy and engineering through forward-looking investigation and development of energy-efficient bandwidth solutions. Our work spans innovative circuit, signaling, packaging, and interconnect solutions with a 3–5 year technology horizon, grounded in rigorous analysis, hands-on measurement, and a commitment to building a robust intellectual property portfolio. As a Principal Signal Integrity Engineer , you will be a core technical contributor on a deliberately small, senior team united around the goal of preparing high-speed interface innovations for high-confidence product adoption. What You’ll Work On Micron’s Interface Pathfinding team investigates and validates novel interconnect and signaling solutions for high-speed memory and die-to-die interfaces. The signal integrity scope is broad and analytically deep — spanning electrical modeling, channel analysis, and substrate evaluation — with an emphasis on original analysis rather than execution of established playbooks. Key signal integrity domains include: Interconnect Modeling — Generating an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description As an EMI / Signal Integrity Qualification Engineer/Senior Engineer in Micron’s Global Quality department, you will measure the electro-magnetic properties of Micron’s DRAM or NAND products. You will also validate their signal integrity. This includes defining test methods and specifications, specifying and maintaining laboratory equipment, understanding and applying relevant automotive quality standards such as AEC Q100, and ensuring on-time execution of measurements and data analysis. You will provide functional guidance to laboratory technicians to ensure accurate, timely data collection. You will also collaborate with Technology Development, Product Engineering, and QRA teams to resolve failing/marginal test results, and to ensure that test methods meet company, automotive, and customer needs. You will also be expected to drive continual improvement, both for efficiency and effectiveness, including using AI tools to improve data analysis, documentation, workflow efficiency, and engineering decision support. You will have the opportunity to contribute to innovation at Micron by developing new test methods to keep pace with Micron’s rapidly changing products, solving problems to enable new product introduction, publishing technical papers internally and externally, and sharing knowledge with engineering peers. Responsibilities & Tasks Lead RF package component and SSD qualification testing, including measurement execution, data analysis, and reporting. Develop, validate,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design and conduct laboratory experiments for SI and PI characterization of Micron components (wafer-, package-, and board-level), providing feedback and guidance to simulation and design teams Provide EMI/EMC measurements, analysis, and mitigation guidance for Micron products and customer systems Improvement and development of internal measurement platforms and methodologies Communicate technical insights to application engineers, designers, other team members, and Micron customers Provide guidance on EMC procedures, techniques, and analysis to Micron Global Quality team members performing compliance measurements Use circuit and electromagnetic simulation tools for analysis and post processing Minimum Qualifications: · BS in EE or similar field with at least 3 years of relevant experience · Strong background in one or more areas of signal integrity, power integrity, EMI/EMC, RF engineering, antenna design, or other fields within applied electromagnetics · Experience with measurements utilizing spectrum analyzers, network analyzers, Time Domain Reflectometer (TDR), near field probes, RF wafer probes, TEM/GTEM cells, and anechoic chambers Preferred Qualifications: · Experience with programming (e.g. Python, Matlab) and scripting lan

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Within the larger SI R&D group, as a Principal Signal Integrity Engineer at Micron, you will be responsible for: Leading the development and analysis of high speed (HS or similar expertise) memory interfaces and power distribution networks (PDN) . Applying AI/ML and data-driven techniques to accelerate Signal Integrity / Power Integrity analysis, build optimization , and engineering decision-making. Applying automation, scripting, and AI-assisted engineering workflows to improve simulation efficiency and coverage. Representing the Signal Integrity R&D team in technical cross-functional collaborative groups , integrating with package build, silicon develop, system invent, product engineering, and marketing departments to ensure overall product performance. Driving and developing SI/PI aspects of future standards (including but not limited to JEDEC, ONFI, and IBIS) through system and product electrical capability exploration. Supporting external customers as needed. Formulating techniques and protocols for SI/PI analysis. Supporting and driving path-finding activities for IO and channel innovation to enable the next generation of memory technologies at higher speeds and densities. Minimum Qualifications PhD or MSEE, or equivalent experience, with at least 5 years of industry experience. Deep experience in Signal and Power Integrity, particularly in areas affecting I/O circui

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define what is possible at the limits of speed and scale. Our architecture team evaluates future interfaces early, using data‑driven analysis to guide product and IO strategy. This role focuses on early‑phase SI architecture exploration. You will independently model, simulate, and assess high‑speed interfaces and translate findings into clear architectural intent and requirements. This role uses AI for work optimization. Responsibilities: Define SI architectural strategies for high‑speed memory and system interfaces Perform early feasibility and scaling analysis for future data rates Build hands‑on channel models across package, board, and system Drive end‑to‑end SI co‑design with IO, package, and system architects Translate SI insights into electrical requirements and architectural constraints Minimum Qualifications: Bachelor’s degree or equivalent practical experience in Electrical Engineering or related field 10&#43; years of experience in signal integrity or high‑speed interface design Strong hands‑on SI modeling and simulation experience Deep understanding of transmission lines, jitter, loss, and crosstalk Preferred Qualifications: Master’s degree in a related technical field Experience with memory interfaces or high‑speed IO standards Background in architecture or pre‑silicon exploration roles Strong communication of complex SI trade‑offs to leadership Experience using AI/LLM productivity tools. <p style="text-

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures. This role is remote role open to any location in the U.S. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts. Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off. Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity). Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs. A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues. What We Need Lead Die-to-Die (D2D) physical implementation and closure, taking high-spe

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever ! The Heterogeneous Integration Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications. Using Through Silicon Via (TSV) technology, we stack multiple DRAM chips with a high-speed interface die, significantly increasing memory density and bandwidth for next-generation AI/ML accelerators and high-performance computing platforms. Our designs target the industry's lowest power-per-bit and highest bandwidth, enabling the most demanding compute workloads. We are seeking a SI/PI Engineer in HBM Build Architecture to develop high-quality SI/PI analysis for interposers, packages, and silicon channels. This work contributes directly to HBM build sign-off and product success. You will be involved in complex, multi-disciplinary SI/PI initiatives spanning multiple HBM product generations — from early interposer channel analysis and equalization co-design, PDN architecture, and system PI analysis. You will ensure Micron's HBM SI/PI architecture remains the industry benchmark for signal quality, power delivery integrity, and interface reliability. This role supports the design and deployment of AI-enabled solutions that improv

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities Perform pre-layout and post-layout signal integrity simulation for high-speed interfaces, including DDR4/DDR5, PCIe Gen3–Gen5, and 100G/400G/800G Ethernet. Evaluate channel loss, PCB material, stack-up, IC placement, and routing constraints during the early design stage. Build and analyze end-to-end channel models, including PCB traces, vias, connectors, cables, packages, and IC models. Optimize high-speed channel structures, including vias, anti-pads, connector launches, cables, and routing topology. Analyze insertion loss, return loss, crosstalk, impedance discontinuity, jitter, eye diagram, and BER performance. Define PCB layout guidelines and routing constraints for high-speed interfaces. Work with EE, layout, mechanical, vendor, and validation teams to review designs and resolve SI issues. Support simulation-to-measurement correlation using VNA, TDR, oscilloscope, BERT, or compliance test results. Qualifications Bachelor’s degree or above in Electrical Engineering, Electronics Engineering, or a related field. 5+ years of experience in high-speed signal integrity simulation and PCB channel design. Hands-on experience with Ansys simulation tools, such as HFSS, SIwave, Q3D, or AEDT. Familiar with high-speed interfaces, including: DDR4,DDR5 PCIe up to Gen5 IEEE 802.3by / 802.3bm / 802.3bs / 802.3cd,100G / 400G /

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications! Our ultimate goal is to deliver the lowest power per bit solutions in the industry! Position Overview: We are searching for an HBM IO Design Architecture Engineer. This role will focus on HBM IO / TSV IO design and analysis including electrical modeling, Signal Integrity (SI) and Power Integrity (PI) analysis, and design optimization across the HBM development cycle. The ideal candidate brings hands-on experience in design execution, simulation to silicon correlation, and cross-functional methodology development, and embraces AI-driven analysis and data-driven decision making to accelerate quality improvement cycles. Responsibilities will include, but are not limited to: High-speed IO design architecture for HBM products Define and standardize IO design quality process from architecture to silicon Define IO architecture, TSV IO performance targets, and design quality requirements for future HBM products. Develop IO and TSV modeling methodologies to support architecture tradeoff analysis, SI/PI evaluation, and design optimization. Drive simulation-to-silicon correlation and post-silicon learning feedback to improve design quality across HBM product generations. Leverage AI Assisted analytics to accelerate root cause identification from comp

Experienced or Senior Digital Design Engineer Company: The Boeing Company Boeing Defense, Space & Security (BDS) seeks a Digital Design Engineer to join our team in Huntsville, AL and play a vital role in the Patriot Advanced Capability-3 (PAC-3) program, one of the world's most advanced air and missile defense systems. This is your opportunity to work in a dynamic environment where your skills will directly contribute to protecting critical assets and ensuring mission success. If you are passionate about defense technology and want to make a real impact, we want to hear from you! Position Responsibilities: Design high speed digital circuits and perform signal integrity analysis Focus on electronic systems and electrical design, simulation and verification/validation testing of high-speed printed circuit boards (PCB) throughout full product development cycle Providing design guidelines and support for system architecture design, board layout, product bring-up, debug, validation, and factory builds This position requires obtaining a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim U.S. secret clearance Pre Start and final U.S. secret clearance Post Start is required. Basic Qualifications (Required Skills/Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement 3 or more years of related work experience Experience in digital circuit design Preferred Qualificatio

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview The Non-Volatile Engineering Group (NVEG) at Micron develops memory products that are best-in-class in die size, performance, reliability, and power! Our mission is to innovate and deliver groundbreaking non-volatile memory solutions such as NAND. As the pace of technology accelerates, NVEG is aggressively embedding AI across every stage of the design flow — from circuit exploration and layout optimization to silicon debug and specification analysis — and we are looking for engineers who not only use AI in their daily work but also actively reshape our engineering workflows to unlock AI’s full potential! Position Overview As a Principal Design Engineer in NVEG, you will architect, design and sign off the high-speed IO interface of next-generation NAND flash, moving data between the NAND die and the host controller at multi-GT/s rates under tight power, area and signal-integrity limits. You will own IO blocks end to end, from spec and architecture through circuit design, layout guidance, verification and silicon correlation. You will set IO architecture direction across products, lead task forces, and make the key trade-offs that hit aggressive data-rate and power targets. AI is a central pillar of how this team works: you will use AI tools daily and reshape wor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: • Own and deliver critical HBM IO blocks and subsystems from architectural definition through circuit and RTL implementation, verification, tape-out, silicon bring-up, and post-silicon debug, including interfaces supporting future CPO systems. • Define HBM PHY, controller-to-PHY, die-to-die, clocking, training, calibration, power-management, error-handling, and test requirements for advanced heterogeneous systems. • Drive robust, high-performance builds by balancing bandwidth, latency, power, area, reliability, electrical signal quality, power stability, yield, and manufacturability trade-offs. • Lead architecture and design of analog, mixed-signal, and digital interface functions used in high-speed memory subsystems. • Partner with package, interposer, physical design, signal integrity, power integrity, and thermal teams to optimize interface implementation across 2.5D and 3D systems. • Lead root-cause analysis and resolution of complex pre-silicon and post-silicon issues across circuit design, RTL, architecture, process, package, interposer, and system interactions. • Serve as technical project lead for one or more advanced interface programs, coordinating execution across architecture, design, layout, verification, validation, packaging, test, and product engineering teams. • Define and communicate technical priorities, interface specifications, execution plans, risks, dependencies, and schedule impacts. • Work with internal teams, customers, IP pr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, including Datapath, bias networks, IO front ends, and reference circuits, ensuring robust operation across PVT, low noise coupling, and high matching accuracy 3-12 years of solid hands-on experience in custom analog and high-speed layout design, with proven expertise in implementing and delivering critical analog blocks and LPDDR/high-speed interfaces at advanced technology nodes Lead high-speed LPDDR (LPDDRx) interface layout execution , solving complex signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes Architect and implement scalable array-based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and multi-channel scalability Drive integration of custom digital and mixed-signal blocks within the PHY (training logic, calibration engines, test/debug circuitry), ensuring optimal clocking, congestion management, and isolation from sensitive analog regions Lead layout-aware co-design with circuit teams , enabling early closure of timing, noise, IR, EM, and parasitic effects, and influencing design decisions from a layout perspective Establish robust power distribution, grounding, and isolation strategies , including guard rings, deep N-well usage, decoupling, and domain separation for

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. Micron is seeking a Design Infrastructure Engineer to build, enable, and scale characterization infrastructure and deliver generated IP to multiple advanced memory and logic developments. This position includes characterizing both standard and custom cells across various process technologies. These encompass Micron internal nodes as well as external foundries, such as TSMC. The position supports multiple HBM product lines, including HBM DRAM dies, Logic dies (JEDEC and custom variants), and advanced 3D HBM architectures. You will work where circuit build, EDA infrastructure, and silicon validation readiness meet. You will develop robust, scalable, and high-quality characterization flows. These flows directly affect timing closure, power modeling, and product quality for next-generation HBM programs. Responsibilities: Develop and sustain scalable infrastructure for standard cell and custom cell characterization, encompassing timing, power, noise, and signal integrity modeling. Build reusable, a

What We’re Looking For: We’re looking for engineers to contribute to the thermomechanical, electrical and mechanical design and assembly of the IO modules that attach to our A-0 and A-1 wafers. Ideal Background: Deep understanding and hands-on experience with signal integrity signoff for copper and electro-optic connector interfaces Hands-on experience with mechanical aspects of electrical and electro-optic connectors Experience with bringup of connectorized links and systems Nice to Have: Experience and understanding of sockets and socketed connectors Experience with co-packaged copper and co-packaged optics Experience with high density optical modules Experience with XPO optical pluggable form factors