Simulation Engineer Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Front End Design Verification Engineer to help verify the fetch unit for our next generation of high-performance RISC-V CPU cores. You’ll work on the logic responsible for keeping the processor fed with the right instructions at the right time—from instruction fetch and prediction through decode and dispatch. You’ll partner closely with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, debug complex failures, and ensure the front end behaves correctly across a wide range of workloads and corner cases. This is an opportunity to make a direct impact on the performance and correctness of a high performance out-of-order CPU. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on verification engineer who enjoys digging into complex processor behavior and finding subtle bugs. Comfortable working with CPU front-end concepts such as instruction fetch, branch prediction, instruction decode, queues, and dispatch. A strong problem solver who can move between specifications, RTL, simulations, and waveforms to ide

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Senior Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products. This role collaborates globally across design, verification, product engineering, test, probe, process integration, assembly, and marketing to ensure manufacturable, high‑quality, cost‑optimized solutions. The position drives innovation in future memory generations and contributes to silicon‑to‑system development in a dynamic engineering environment. Responsibilities Design digital, analog, and memory core circuits using CMOS logic and transistors, implementing device specifications from concept to solution. Utilize AI-Enabled tools to assist with schematic editing, data collection and layout floorplan. Create optimized floorplans for circuit placement, routing, power delivery, sense margins, array timing, and die size, including layout leadership. Conduct circuit simulations using FINESIM, HSPICE, and VERILOG; analyze power, performance, reliability, and parasitic impacts. Validate builds through reticle experiments, tape‑out revisions, and simulation‑to‑silicon correlation, identifying required schematic edits. Prepare and maintain design documentation while contributing to best‑known practices and departmental training. Collaborate with global build, verification, product engineering, test, probe, process integration, assembly, and marketing teams to ensure manufacturability and quality. <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a member of the HIG HBM Media Health HVM team, you will embody an outstanding approach to Next Generation HBM Product driven by important metrics: Quality, Cost, Cycle Time, and Scale. You will work closely with various teams within and outside of HBM to achieve strategic and operational goals. Key Responsibilities Optimized Test Coverage: Ensure optimized test coverage on all current and future HIG HBM design architectures and process nodes to maintain effectiveness and efficiency in high-volume manufacturing. Encouraging Innovation: Motivate innovation and inspire changes that will help Micron maintain a technical advantage over its competition, ensuring Micron’s competitive edge in the market. Product Development and Validation: Develop, validate, characterize, and qualify Micron’s next-generation HBM products, ensuring reliability and market readiness. Support for New Product Design Validation: Provide support for design verification and in-depth circuit analysis of new products using CAD tools and Verilog simulations. Yield Improvement and Cost Reduction: Improve manufacturing test yields, reduce test time, and resolve yield-related issues, contributing to cost reduction and meeting yield targets. Root Cause and Resolution of Qual and RMA Device Issues: Identify and resolve issues related to device qualification and return material authorization, ensuring product quality. Process Conversions and HVM: Recommen

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Engineer in the High Bandwidth Memory (HBM) Media Health (MH) team, you will work with Fab, Yield Improvement, Design, and other engineering groups passionately focused on HBM. You will develop, deploy, optimize, and innovate test strategies for Micron's DRAM in HBM products. The team acts as a key partner of these engineering groups and specialties, focusing on innovating new and improved test strategies and features. You will guide development for Probe (wafer level test), Burn-in, and ATE test code and testing techniques used to validate and ensure device performance. You will assist in debugging code and aiding other specialists in the characterization of applicable HBM devices. In this role, your additional responsibilities include an in-depth understanding of general device functionality specific to HBM products as well as schematics and signal integrity. Responsibilities: Work with Design Engineering to run simulations pre-silicon to validate DFT circuits and test modes as well as communicate design issues found. Work on pre-silicon tasks with MH and test teams to define required tester resources. Work with Test Engineering and HBM Product Engineering to ensure specific product requirements or limitations are comprehended, leading to silicon performance matching expectations. This work includes test program debug, examination of data, and test development. Support the fabrication sites and Process Integration through test development to increase effective process feedba

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Principal Design Engineer in Micron’s NVEG (Non‑Volatile Engineering Group) organization will own and evolve the timing-critical circuitry between the NAND array and page buffer. This role is for a designer who is equally strong in architecture, transistor-level implementation, and physical aware timing closure – and who can lead technical direction across teams to deliver robust, scalable datapath solutions. You will drive designs that directly impact throughput, timing margin, power and yield, partnering closely with page buffer, array device, clocking, physical design, test, and product teams. Responsibilities Own internal NAND datapath circuits including array redundancy circuits, wave pipeline / pulse based datapath arctitechture and data line sensing circuits. Define scalable datapath architecture supporting multi-plane and high-parallelism operation. Define and analyse clock/data timing schemes for long interconnects and large-array topologies. Lead timing adjustment and skew management strategy. Drive layout-aware circuit design with attention to: matching/symmetry for sensing paths, shielding/guarding for sensitive nodes. Parasitic-aware sizing and RC-driven timing closure. Array pitch constraints, blockages and repeatable layout templates. Partner tightly with layout to review critical routes and implement practical fixes. Perform SPICE/Fast-SPICE simulations across PVT, aging and variability via Monte Carlo. Define characterization structures and debug

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Design Engineer, you will build the future of memory by architecting and delivering high‑performance DRAM circuit compositions for advanced technology nodes. In this highly visible technical leadership role, you’ll develop innovation across building, layout, verification, and silicon validation. You will collaborate closely with multi-functional teams to deliver scalable, manufacturable solutions for next-generation memory products. Your work will directly influence performance, power, reliability, and time‑to‑market for Micron’s groundbreaking memory technologies. Responsibilities Design and optimize DRAM circuits spanning digital, analog, and memory core subsystems to meet aggressive power, performance, and reliability targets Develop and refine floorplans, routing strategies, power delivery networks, sense margins, timings, and die‑size tradeoffs Perform advanced circuit simulations using FINESIM, HSPICE, and VERILOG, analyzing speed, power, noise, and long‑term reliability Model parasitics, verify power and signal integrity, and support validation, reticle experiments, and tape‑out revisions Drive simulation‑to‑silicon correlation, identify gaps, and recommend schematic and layout improvements Lead technical reviews, documentation, and best‑practice standardization across design and layout teams Coordinate and manage layout and build resources, tracking breakthroughs and resolving critical path issues S

Zoox is looking for a Senior Signal Integrity and EMC Engineer to ensure the electrical reliability, signal fidelity, and compliance of our complex autonomous vehicle systems. In this role, you will own the end-to-end strategy for vehicle-level signal integrity, RF/wireless performance, and EMC. You will work within a multi-disciplinary engineering team to set rigorous requirements and ensure best practices are implemented from concept to production. You will serve as the domain expert on a variety of high-speed digital and RF design topics that bring our hardware to life safely and reliably. In this role, you will: Lead the development, implementation, and validation of vehicle-level signal integrity, grounding, and shielding strategies. Maintain rigorous technical requirements and EMC specifications applied across all electrical and electronic systems on all vehicle platforms. Define and maintain vehicle-level RF performance requirements, establishing specifications for all transmitters, receivers, and antenna systems to mitigate the electromagnetic impacts of physical vehicle installation on wireless communication. Perform and/or oversee signal integrity and power integrity (SI/PI) simulations and analysis for critical high-speed interfaces and power distribution networks. Simulate RF performance of all antennas, transmitters, and receivers as installed in a vehicle during the vehicle design phase to drive integration alignment. Collaborate with cross-functional design teams to ensure best practices for signal integrity, RF design, and EMC are implemented. Lead design reviews to identify and remediate vulnerabilities early to meet project milestones. Develop and execute validation plans for vehicle-level signal integrity, RF/wireless performance, and EMC, including radiated and conducted emissions/immunity. Troubleshoot and resolve complex signal integrity, RF, and EMC issues discovered during design, validation, and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The DRAM Technology group at Micron Technology develops and validates advanced memory solutions that enable the transformation of information into intelligence. The team operates in a collaborative, inclusive, and globally distributed environment, partnering closely with design, product, test, process, manufacturing, and quality organizations to deliver industry‑leading DRAM technologies. The Design Validation Product Engineer supports the validation of new DRAM products by focusing on real‑silicon behavior through bring‑up, characterization, and debug. This role builds a strong technical foundation in DRAM architecture, semiconductor devices, and validation methodologies while working closely with multi-functional engineering teams. Responsibilities Support DRAM design validation through silicon bring‑up, characterization, and validation testing of new memory products Analyze electrical and functional data to identify trends, marginalities, and failure mechanisms Assist with debug of validation issues using simulations, test results, and laboratory measurements Use engineering lab equipment and testers to characterize device behavior and performance Document validation results, test coverage, and observed behaviors while collaborating with design, test, manufacturing, and quality teams Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field Strong fundamentals in digital logic,

Perplexity is seeking a highly skilled, experienced and hands-on Offensive Security Engineer to join our dynamic security team, taking an adversarial approach to hardening Perplexity's infrastructure, applications, and AI systems. You'll plan and execute red team operations, penetration tests, and attack simulations across our cloud infrastructure, web and mobile applications, AI/ML pipeline, and corporate environment—finding real vulnerabilities before adversaries do and working directly with engineering teams to drive remediation. Responsibilities Plan and execute red team and purple team engagements simulating advanced threat actors across cloud infrastructure (AWS, Kubernetes), endpoints, and application surfaces Conduct continuous penetration testing of web applications, APIs, mobile clients, browser extensions, cloud infrastructure, and internal services Assess AI/ML-specific attack surfaces including prompt injection, model exfiltration, agent abuse, tool-use exploitation, and MCP security boundaries Develop and maintain custom offensive tooling, exploits, and automation to improve the efficiency and coverage of security testing Perform open-scope adversary simulations that test detection and response capabilities end to end, collaborating closely with the defensive security team Drive threat modeling sessions with engineering teams to identify and prioritize attack vectors in new features and architectures Deliver clear, actionable findings to both technical and executive audiences; partner with engineering to validate remediations Contribute to the security of CI/CD pipelines, supply chain integrity, and secrets management through offensive assessment Stay current on emerging attack techniques, vulnerability research, and adversary tradecraft; bring external perspective into Perplexity's security strategy Qualifications 5+ years of hands-on experience in offensive security, red teaming, or penetration testing Deep technical expertise in at least two of: clo

Join us in building the future of finance. Our mission is to democratize finance for all. An estimated $124 trillion of assets will be inherited by younger generations in the next two decades. The largest transfer of wealth in human history. If you’re ready to be at the epicenter of this historic cultural and financial shift, keep reading. About the team + role We are building an elite team, applying frontier technologies to the world’s biggest financial problems. We’re looking for bold thinkers. Sharp problem-solvers. Builders who are wired to make an impact. Robinhood isn’t a place for complacency, it’s where ambitious people do the best work of their careers. We’re a high-performing, fast-moving team with ethics at the center of everything we do. Expectations are high, and so are the rewards. The Red Team team’s mission is to proactively identify and simulate real-world threats against Robinhood’s platforms, properties, and people. Through red teaming and adversarial simulations, the team evaluates security controls, uncovers vulnerabilities, and helps continuously strengthen Robinhood’s overall security posture in close partnership with Detection & Response, Physical Security, and Engineering. As a Staff Offensive Security Engineer, you will take a hands-on role in designing and executing stealthy adversarial simulations to validate assumptions and uncover gaps in detection and response. You’ll leverage threat modeling, penetration testing, and research-driven techniques to emulate sophisticated attackers, while collaborating cross-functionally to improve defenses and shape more secure systems. This role is based in our Toronto, Canada office(s), with in-person attendance expected at least 3 days per week. At Robinhood, we believe in the power of in-person work to accelerate progress, spark innovation, and strengthen community. Our office experience is intentional, energizing, and designed to fully support high-performing teams. What you’ll

NVIDIA Networking division is a leading supplier of innovative end-to-end InfiniBand and Ethernet connectivity solutions and services for servers and storage. We offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. Our products optimize Data Center performance and deliver industry-leading bandwidth and scalability. In addition, we serve a wide range of sectors including high performance computing, enterprise, Data Center, cloud computing and Web 2.0. We are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry. Our product line is focused on delivering the most optimized Ethernet solutions for industries like Media and Entertainment as well as any other industry that can benefit from our DataStream and TCP/IP acceleration. What you will be doing: Drive multiple early-stage design concepts of Test Equipment & fixtures while working in fast-paced product development cycles. Independently lead Test Equipment & fixtures design from concept, through detailed design, and support it during Bring-up, Qualification and Mass-Production phases. Participate and lead design and design reviews of Test Equipment & fixtures by using our CMs (Contract Manufacturers) as the designers Collaborate in research of groundbreaking technologies, materials, and processes with other groups to bring in creative ideas that address evolving needs. What we need to see: B.Sc. in Mechanical Engineering or higher degree. 5&#43; years of experience in classical mechanical design of mechanisms, jigs, fixtures, products and machines development. Knowledge and experience in automation (pneumatics XYZ motion systems, etc) and in design of machining and sheet metal parts Knowledge and experience in static analysis and simulations.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a senior engineer to improve the reliability, performance, and user experience of the high-performance computing infrastructure that supports silicon development. This role sits at the intersection of EDA, distributed systems, CI/CD, and developer productivity. You will help engineering teams run simulations, verification, coverage, and other silicon-development workloads with fewer failures, shorter feedback cycles, and better operational visibility. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Hold an advanced engineering degree (BS, MS, or PhD in EE, ECE, CS, or related field) paired with over seven years of hands-on industry experience. Bring expertise in Git branch strategies, merge conflict resolution, operational failure debugging, and software engineering repository management practices. Possess practical working knowledge of SQL databases, data query optimization, and modern structured data technologies. Leverage AI-assisted development tools and agentic workflows to solve complex technical problems, enhance automated testing, and streamline

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As the Senior Manager of Security Operations, you will lead and scale Everpure's global Detection Engineering and Cloud Incident Detection & Response (CIDR) teams. You will own the mission of transforming SecOps into a proactive, intelligence-driven defense engine that measurably reduces risk across cloud, SaaS, infrastructure, and endpoint environments. Partnering closely with GRC, Infrastructure, Product Security, and Engineering leadership, you will establish operational work plans, detection standards, and response strategies that safeguard the Everpure Platform against sophisticated global threats. WHAT YOU'LL DO Direct Detection Engineering & Incident Response Strategy: Establish operational objectives, work plans, and SLAs across threat detection, automated response workflows, and incident triage to continuously optimize Mean Time to Detect (MTTD) and Mean Time to Respond (MTTR). Champion Threat-Informed Detection & Validation: Lead the deployment and continuous refinement of a high-signal detection inventory mapped to MITRE ATT&CK, validating control efficacy through automated simulations, red/purple team exercises, and threat hunt findings. Streamline Telemetry Ingestion & Automation: Oversee the architectural ingestion of multi-cloud (AWS, Azure), endpoint, network, and SaaS log sources into SIEM and SOAR pipelines, reducing false positives and accelerating automated remediation. Lead

About Hark Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory. We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world. To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems. About the Role At Hark, you'll lead the development for the foundation of agentic reinforcement learning (RL) environments: the digital worlds in which AI agents learn to use software, navigate complex workflows, and act on their surroundings. Our ambition is to simulate the breadth and complexity of the internet, connecting websites, apps, services, and artifacts into rich, stateful environments, with the potential to evolve dynamically over time. This is a chance to shape both the worlds agents learn in and the systems that make learning at scale possible. You'll build environments end-to-end and work closely with researchers to bring them into RL training and evaluation. You'll also develop the infrastructure behind our agent gym, making these environments easy to integrate, reproduce, and scale across heterogeneous execution targets. Responsibilities Build agent environments and simulations end-to-end, including frontend interfaces, backend services, APIs, data models, tools, and realistic workflows used to train and evaluate AI agents. Build the infrastructure that powers our agent gym, including orchestration, sandboxing, packaging, benchmarking, and systems for running environments across heterogeneous targets. Create interconnected simulations w

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. Program Overview Some of our world's grand challenges, from resolving long-open problems in mathematics to designing medicines for neglected diseases, require deep expert judgment that today's AI still lacks. We're working toward an AI scientist, a system capable of the long-horizon reasoning and experimental judgment needed to push the frontier on problems like these. We believe frontier AI, developed safely, can meaningfully accelerate progress across science and engineering. Getting there requires close collaboration with people who have spent years at the frontier of their fields. The Anthropic STEM Fellows Program brings researchers and experts from across science and engineering into Anthropic for four months to take on the grand challenges of their fields with Claude. Working in small pods of Fellows from related fields, you will pair deep domain expertise with our frontier models and internal tooling to define the hardest open problems in your discipline, build the datasets and simulations that let us test and train Claude on them, and find exactly where it falls short. We're looking for Fellows across science and engineering. Prior machine learning experience is helpful but not required. Scientific judgment and a willingness to learn quickly matter more. Our first cohort of more than 20 STEM Fellows across mathematics, physics, the life sciences, and engineering, ran from June to September 2026. The problems they built now feed Claude's training and one of our internal science evaluations. What to Expect: A place in a small pod of Fellows working on related problems in your domain. Your pod meets weekly with Anthropic researc