Advanced Packaging Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s Heterogeneous Integration Group (HIG) is shaping the future of AI and accelerated computing by developing advanced memory solutions! The team focuses on designing and optimizing High Bandwidth Memory (HBM) products for AI/ML, high-performance computing (HPC), and data-centric systems, collaborating across global engineering and product teams to deliver industry-leading performance, power efficiency, and reliability! HBM product family is growing due to high demand from industry-leading semiconductor companies. As an HBM Memory Design Engineer you will work closely with cross-functional teams including Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging, and Technology Development (TD) to analyze and resolve silicon issues across HBM products . You will collaborate with architecture to understand new or updated specification requirements and contribute to the implementation, verification, and maintenance of design updates , supporting both silicon release and ongoing product lifecycle needs. This role requires strong AI driven technical execution and the ability to independently drive complex issues to closure. Responsibilities Design Support: Work on HBM product design and support sustaining design maintenance (ECOs/spec changes). Silicon Debug: Own end-to-end debug of silicon, system, and customer issues, driving root-cause analysis and resolution. Cross-Functional Collaboration: Work closely with DE, PE, TD,

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Overview As a Staff/Senior Process Development Engineer within PDE-CEM, you will leverage advanced semiconductor process characterization, failure analysis, yield analytics, and process integration expertise to accelerate product and technology development. The role focuses on developing robust assembly processes, improving yield and reliability, supporting New Product Introduction (NPI), and utilizing data-driven methodologies to optimize manufacturing performance. The ideal candidate combines strong semiconductor physics knowledge, advanced characterization skills, yield improvement experience, and cross-functional leadership capability to drive continuous process innovation and manufacturing excellence. Key Responsibilities Process Development & Characterization Develop and optimize Process of Record (POR) for assembly and packaging technologies. Establish process windows, process capability targets, and characterization strategies. Apply statistical methodologies including DOE, SPC, JMP, and Six Sigma to characterize and optimize manufacturing processes. Drive early process learning through advanced characterization and failure analysis techniques. Yield Improvement & Problem Solving</

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As FE CPIE CPI PI Senior Engineer at Micron Technology, Inc., you will be responsible for working with global Micron network to drive each silicon node's Packaging Product yield, quality improvement, new product introduction (NPI) through technical expertise, business process management and project execution. In addition, you will be responsible in integrating solutions by connecting cross-functional expertise, standardizing the business process and regularly benchmarking internal and external intelligence to achieve the highest value bits and productivity. In addition, you will leverage AI-enabled engineering approaches, advanced analytics, and digital tools to accelerate problem solving, improve productivity, enhance decision quality, and drive continuous innovation across product yield, quality, and business processes. Responsibilities and Tasks Promote worldwide synergy for improved benchmark performance and efficiency gains through global project management and execution, network BKM leveraging and enhancement, and business process creation and re-engineering. Define strategies to ensure that Packaging Technology and interaction with Front End manufacturing process are fully developed and qualified well ahead of any qualific

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Job Details: Job Description: Designs, develops, sustains, tests, validates, and debugs software to enable specific factory, wafer process, packaging features, capabilities, solutions, and/or reference platforms for Intel manufactured products. May work across multiple layers of the software stack spanning firmware, drivers, operating systems, database platforms, storage platforms, network/firewall, middleware, frameworks, algorithms, automated material handling systems, and/or applications for mission critical distributed enterprise systems spanning a large number of clients/servers and applications across multiple operating systems, specific technology, product/platform, or Manufacturing segment. Integrates, supports, and sustains Factory Automation software systems to ensure reliable and efficient manufacturing operations. Applies advanced troubleshooting techniques to diagnose and resolve automation system issues, minimizing system downtime and improving overall system performance. Drives continuous improvement initiatives to achieve automation system health goals, enhance system reliability, and support emerging manufacturing capability requirements. Serves as the automation subject matter expert for designated automation systems, representing system integration needs and collaborating with cross-functional and cross-site teams to drive solutions. Supports automation system monitoring tools, system validation, software testing, troubleshooting, and software quality control activities. Partners with Virtual Factory teams and relevant stakeholders to facilitate knowledge sharing, issue resolution, and continuous improvement across manufacturing sites. Provides 24x7 production support through a rotating day and night shift schedule, working 12-hour shifts (AA, BB, CC, DD rotation) to ensure continu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s High Bandwidth Memory (HBM) Design Architecture organization, where we push the limits of memory technology every day. Our team works across global, multicultural engineering groups to build next-generation HBM solutions that power AI and machine learning. We believe the best ideas come from collaboration, curiosity, and a shared drive to innovate! This role plays a critical part in ensuring the reliability of Micron’s most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design through high-volume manufacturing, working hands-on with silicon, layout, and foundry partners. If you enjoy solving deep technical problems and influencing product robustness at scale, this role offers both impact and growth. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards Enable ESD protection circuits and latch up safe layout practices across designs and technologies Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams<

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary We are seeking a highly motivated Failure Analysis Engineer to join our Product Failure Analysis (PFA) Laboratory. The successful candidate will be responsible for conducting failure analysis, root cause investigations, and advanced package characterization to support product development and yield improvement. This role requires strong analytical skills, hands-on laboratory experience, and the ability to collaborate with cross-functional teams in a fast-paced semiconductor environment. Qualifications Education Bachelor's or Master's degree in: Materials Science & Engineering Electrical Engineering Electronics Engineering Mechanical Engineering Chemical Engineering Physics, Chemistry, or related technical disciplines Experience in one or more of the following areas is preferred: Wafer Fabrication Assembly and Packaging Product Engineering Yield Enhancement Failure Analysis Laboratory Advanced Packaging Technologies Responsibilities Perform electrical and physical failure analysis of semiconductor devices and packages. Conduct root cause investigations and provide technical recommendations. Develop and execute analytical plans to support engineering requests. Interpret analytical results and communicate findings effectively. Collaborate with Process, Product, Quality, Reliability, and Manufacturi

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a PDE MRDA KEG Engineer / Senior Engineer , you will be responsible for developing, qualifying, deploying, and sustaining advanced defect inspection and metrology solutions that support New Product Introduction (NPI), HBM technology ramps, and High Volume Manufacturing (HVM). You will drive inspection capability readiness, equipment performance improvement, and defectivity reduction through close collaboration with cross functional team. The role requires strong expertise in semiconductor manufacturing, defect inspection technologies, data analytics, equipment qualification, and cross-functional problem solving to enable industry-leading process control and yield performance. Inspection Technology & Equipment Ownership Manage advanced inspection and metrology platforms throughout package development and manufacturing. Develop technology roadmaps and capability strategies to meet future packaging requirements. Drive equipment lifecycle management, capacity planning, and technology insertion activities. Equipment Qualification & Deployment Lead tool installation, qualification (TIQ), release, and production readiness activities. Establish equipment acceptance criteria, qualification methodologies, and deployment pla

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we're not just designing chips. We're building the physical architecture that powers artificial intelligence, accelerates cloud computing, enables autonomous vehicles, and connects the world through mobile and edge devices. Every breakthrough in AI — from large language models to next-generation data centers — runs on memory. And every bit of that memory lives inside a package that someone like you designs! We're looking for a Senior Package Design Engineer who is passionate about sadvanced semiconductor packaging and ready to lead at the intersection of silicon, system, and scale. This is a high-impact, highly visible role where you'll work across the full product lifecycle — from early-stage co-design with silicon teams all the way to High Volume Manufacturing (HVM). If you thrive where precision meets innovation, where your decisions shape products reaching millions of users worldwide, and where your expertise directly influences how the AI era unfolds — this role is for you! Responsibilites: Lead Co-Design from Silicon to System - Partner with silicon design, Business Units, customers, and package architecture teams to define new product concepts from the earliest stages of chip development - Optimize die floorplans, interconnection schemes, and package architectures — from concept to HVM - Drive trade-off studies and architecture decisions for advanced DRAM products targeting AI/D

As Manager, Sensor Integration/Cleaning HW, you will lead a team responsible for ensuring Zoox vehicles can operate safely and reliably in real-world environments. You will manage a multidisciplinary team of engineers designing, integrating, validating, and launching sensor assemblies and sensor cleaning systems that maintain the performance of our autonomy sensors across a wide range of environmental conditions. You will drive your team's engineering solutions and program execution to ensure sensors remain within operational specifications, minimize contamination-related failures, optimize for supply chain and volume manufacturing, improve vehicle availability and serviceability, and support the scalable deployment of Zoox autonomous vehicles. In This Role, You Will Lead, mentor, and grow a team of mechanical, electrical, and systems engineers developing sensor assemblies and sensor cleaning systems for Zoox's autonomous vehicle fleet. Own program delivery for sensor integration and sensor cleaning hardware, from concept through validation, launch, and fleet support. Set technical direction and review key design decisions across mechanical packaging, electrical integration, and system-level architecture for sensor and cleaning subsystems. Partner with sensor performance, perception, test, manufacturing, and quality teams to ensure designs meet performance, reliability, and manufacturability requirements. Manage program scope, schedule, and resourcing across multiple concurrent sensor integration and cleaning projects. Drive cross-functional design reviews, DFMEA/PFMEA processes, and validation planning to de-risk programs ahead of production. Represent the team in front of engineering leadership, communicating program status, technical tradeoffs, and risks. Recruit, develop, and retain engineering talent, and build a strong culture of technical rigor and ownership within the team. </di

NVIDIA is looking for a hands-on Solutions Architect Manager to lead a team of GPU, networking & software solution architects and engineers. Do you want to build and lead a group that designs, debugs, and deploys new AI hardware and software technologies into production in customer data centers? As part of the NVIDIA SA organization, you will drive people and technical leadership for end-to-end solutions deployments at some of NVIDIA's most strategic technology customers, while directly contributing to designs and deep-dive debugging and shaping our product roadmap with customer feedback. What you will be doing: Recruit & manage a team of solutions architects, system/network and software engineers focused on large-scale GPU and AI networking deployments. Set priorities, allocate resources, mentor, and ensure high-quality customer delivery across multiple concurrent projects - while remaining directly involved in key technical reviews, design decisions, and critical debug efforts. Provide deep subject-matter expertise in advanced GPU and network systems and serve as the senior technical point of contact for strategic customers. Personally lead and guide complex compute/network configuration and performance debugging, working side-by-side with your team to deliver performant, reliable clusters. Guide your team as they lead network / compute / software architecture discussions, and support server, network, and cluster bring-up, including on-site data center work where needed. Systematically collect and synthesize customer-specific requirements across your portfolio. Partner with GPU/Network Systems Engineering, Product Management, and Sales to influence roadmap priorities and packaging of reference designs and solutions. Demonstrate SME in advanced GPU & network systems and be a trusted technical advisor to NVIDIA's strategic customers. Bring customer-sp

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As part of the Customer Engineering Technical Leadership (CETL) function within HIG PSE, the Technical Leader will serve as a key technical interface between external customers and internal engineering teams. In conjunction with CIL (Customer Integration Lead), this role requires deep technical engagement to understand customer application requirements and align them with internal HBM design, product engineering, and manufacturing processes (Front-End and Back-End). The position emphasizes technical problem-solving, multi-functional teamwork, and driving integration success for advanced HBM products. Develops and deploys AI systems that help automate processes and tackle technical challenges. Responsibilities: Develop a strong understanding of customer system architecture, application requirements, and integration challenges. Translate customer technical needs into actionable requirements for internal design, product engineering, and manufacturing teams. Provide technical mentorship on HBM architecture, signal integrity, thermal solutions, and packaging strategies. Develops and deploys AI (artificial intelligence) systems that help automate processes and tackle technical challenges Work closely with internal teams across front-end/back-end process engineering, product development, and manufacturing to ensure seamless integration. Support design reviews, failure analysis, and yield improvement initiatives tied to customer requirements. </ul

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) HBM Architecture team develops next-generation High-Bandwidth Memory (HBM) solutions that power AI, high-performance computing, cloud infrastructure, and advanced networking systems. The team works across architecture, design, verification, packaging, product engineering, and technology development to evaluate innovative memory architectures and deliver scalable, high-performance semiconductor solutions. As an HBM Design Architect, New College Graduate, you will contribute to the evaluation and development of future HBM and DRAM architectures. Working with experienced architects and engineering teams, you will analyze system and block-level design tradeoffs related to performance, power, area, thermal behavior, reliability, and manufacturability. This role provides an opportunity to leverage AI, Large Language Models (LLMs), and data-driven engineering methodologies to accelerate architecture exploration and improve decision-making. Responsibilities Analyze HBM and DRAM architectures using analytic