Architect Subsystem Jobs

What We’re Looking For: We’re looking for architects to own key blocks on the A-0 and A-1 systems. This is a role with ownership of an entire sub-block, and you will need to understand how it fits into the entire system and work with other architects and architecture leaders to integrate it into the broader system. Ideal Background: Hands-on experience in owning and delivering the architecture of a block that was part of a larger chip/system. Understanding and hands-on experience in the design of AI accelerators Experience working with microarchitects in the implementation and verification of said block Nice to Have: Experience with the physical design process of the block you owned Experience with large die area chips Experience with multi-die and multi-package chips and systems

What We’re Looking For: We’re looking for memory subsystem architects to contribute and own aspects of the memory subsystem for the largest and highest bandwidth memory system ever built to date. This includes the distributed memory fabric, memory controllers, interface with the XPUs/compute complex, etc. Ideal Candidates: Ideal candidates will have: Deep knowledge and hands-on experience in the design and implementation of memory sub-systems Understand LLM inference workloads and what the impact of that for the memory subsystem is Understand the benefits and limitations of memory tiering for various workloads Nice to Have: Experience with CXL and other memory pooling protocols Experience with design and implementation of memory controllers Experience with processing in memory and other “unique” memory subsystem projects and efforts

Job Details: Job Description: About the Role The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. We are seeking a Senior SoC Compute & Memory Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms. This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments. What You’ll Do Key responsibilities will include but not limited to: Cache Hierarchy and Coherency Architecture 1. Define and evolve multi-level cache hierarchy (private/shared caches, system-leve

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As a Sr. Solution Architect you will own the product definition, technical guardrails, and lifecycle strategy for the hardware components and high-performance networking fabrics powering Everpure’s FlashArray and FlashBlade platforms. Partnering closely with Engineering, Supply Chain, and Field leadership, you will convert complex compute , chassis, and interconnect innovations into scalable, resilient platform capabilities. By defining reference architectures and validating real-world system performance, you will directly drive the commercial readiness, cost efficiency, and operational excellence of our flagship storage portfolio. WHAT YOU'll DO Subsystem Lifecycle & Roadmap Ownership : Define and drive product requirements, qualification criteria, and multi-year lifecycle roadmaps for FlashArray and FlashBlade hardware subsystems ( compute , chassis, interconnect) and networking fabrics (Ethernet, Fibre Channel

What We’re Looking For: We’re looking for a lead architect to own a large portion of the system architecture of the A-0 and A-1 products. Ideal Background: An ideal candidate will have: Experience leading the architecture of an entire system or subsystem (eg chip, board, die, package) Deep understanding of AI workloads like LLM inference at workload levels and its system level implications Experience with large multicore architectures Nice to Have: Experience with physical design process of large-die area, advanced node chips Experience with multi-die designs such as MCMs and interposer designs

About the job Shape the SoC architecture behind Graphcore's next generation of AI acceleration platforms. Graphcore is expanding its Silicon Architecture Team in Bristol to deliver complex AI compute platforms. As a SoC Architect, you will define how critical subsystems are specified, modelled and integrated. You will turn product requirements into architecture choices across interfaces, interconnect, memory and platform behaviour. Your work will guide implementation, validation and trade-offs across multiple chip programmes. You will work with processor, SoC and system architects, plus design, verification, hardware and software teams. Together, you will evaluate IP, resolve integration questions and support silicon bring-up where needed. This is a rare chance to influence real AI silicon while Graphcore scales its contribution to SoftBank Group's AI ecosystem. The team and culture The team owns SoC architecture, subsystem modelling and system-level trade-offs across future AI acceleration platforms. Work moves from requirements to specifications, models, reviews and guidance for implementation teams. People here are expected to take responsibility early and keep decisions moving. You will speak directly with adjacent teams to clarify constraints, challenge assumptions and close open questions. Decisions are made through technical evidence, clear specifications and direct cross-functional discussion. The team values people who think big, act fast and spea

What We’re Looking For: We’re looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations. Ideal Background: An ideal candidate will have: Experience with full ownership of the specs and drove implementation for at least one SoC/die A deep understanding of the process of architecture, microarchitecture and physical design and the ability to coordinate with various groups to drive implementation of SoCs Understanding of SoC interactions with packages, memory subsystems and IO, and ability to work with teams who are responsible for said interacting blocks Nice to Have: Experience with multi-die/multi-chiplet/MCM designs Experience with reticle-max/large-die SoC architecture Understanding of levers available for improving PPA Track record of very high speed A0 silicon delivery

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a System Architect in Advanced System Architecture Group at Micron Semiconductor Products, Inc., you will work with the memory industry's leading architecture team on new concepts that will craft the future of electronic systems around AI, servers, and mobile systems. You should be able leverage Artificial Intelligence for driving the processes and build next gen solutions with AI Supported frameworks. Your Responsibilities Will Include, But Are Not Limited To Delivering architectures and innovative solutions to optimize power and performance of next-generation memory and storage subsystems. Working with design and system architecture teams to identify key system requirements, seek the current bottlenecks and propose novel solutions for a wide range of applications. These activities will entail: Performing system-level simulations of innovative architectures to compare with existing design paradigms, using both open and closed-loop system performance analysis. Developing mode

About the job Shape the SoC architecture behind Graphcore’s next generation AI acceleration platforms. Graphcore is building AI compute systems that push far beyond a single chip. As a SoC Architect, you will define, specify and integrate critical subsystems for complex silicon devices. You will work across processor, SoC and system architecture to turn product requirements into practical design choices. Your work will influence performance, integration, modelling, validation and bring-up. This role is for someone who enjoys deep technical ownership and broad system context. You will help Graphcore deliver multiple AI silicon projects in parallel, at real scale. You will work on interfaces, interconnects and SoC subsystems that sit at the centre of advanced AI platforms. The problems are complex, visible and difficult to find elsewhere. The team and culture The Silicon Architecture team sits at the point where product ambition becomes silicon reality. Architects work closely with design, verification, hardware, software and systems teams. The team is growing because the scope is expanding. You will own meaningful technical areas, move quickly on decisions and keep momentum across groups. Ideas are tested through modelling, specification, discussion and evidence. People are expected to speak up, take responsibility and help others move faster. What we're looking for · Strong understanding of computer architecture, SoC architecture or

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: • Own and deliver critical HBM IO blocks and subsystems from architectural definition through circuit and RTL implementation, verification, tape-out, silicon bring-up, and post-silicon debug, including interfaces supporting future CPO systems. • Define HBM PHY, controller-to-PHY, die-to-die, clocking, training, calibration, power-management, error-handling, and test requirements for advanced heterogeneous systems. • Drive robust, high-performance builds by balancing bandwidth, latency, power, area, reliability, electrical signal quality, power stability, yield, and manufacturability trade-offs. • Lead architecture and design of analog, mixed-signal, and digital interface functions used in high-speed memory subsystems. • Partner with package, interposer, physical design, signal integrity, power integrity, and thermal teams to optimize interface implementation across 2.5D and 3D systems. • Lead root-cause analysis and resolution of complex pre-silicon and post-silicon issues acros

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking an experienced SoC Architect to lead the definition and development of next-generation custom AI silicon for edge deployments. This role will be responsible for shaping the architecture of highly efficient, high-performance SoCs optimized for machine learning inference and on-device intelligence. You will work cross-functionally with internal engineering teams and external ecosystem partners to translate product requirements into scalable silicon solutions, driving execution from concept through delivery. In this role you will: Define the architecture and technical roadmap for custom SoCs targeted for edge applications. Drive system-level tradeoff analysis across compute, memory, interconnect, power, thermal, and cost constraints. Architect energy-efficient ML compute subsystems optimized for inference workloads and real-world deployment environments. Collaborate with internal hardware, software, systems, and product teams to align architecture with platfo

Vehicle Management Systems Architect (Lead or Principal) Company: The Boeing Company Boeing Defense, Space & Security (BDS) Flight Systems Engineering Capability is currently seeking a Lead-Architect Vehicle Management Systems Hardware Engineer to join the Air Dominance Vehicle Management System (VMS), team located in Berkeley, MO. You will work across engineering disciplines to help us design elements of the VMS hardware. You will collaborate with our requirement, hardware, software, and labs teams to implement and test your designs. Mechanical, Electrical, Aerodynamics, and other engineers are all welcome – to succeed in this role, you will need to leverage your area of expertise and quickly learn on the job about other areas to develop capabilities for our Vehicle Management System Computer. You will get to see tangible results of your efforts as you contribute to exciting aircraft development programs in St. Louis. System Architecture Design: Expertise in designing complex, scalable, and modular vehicle management system architectures Aerospace Systems Knowledge: Understanding of aerospace vehicle subsystems, avionics, and integration requirements Hardware Integration: Strong experience with embedded systems, real-time o

Principal Aerospace Systems Architect/Engineer (Directed Energy) Company: The Boeing Company We are seeking a Principal Aerospace Systems Architect/Engineer with deep domain expertise in directed energy (DE) weapon systems to provide technical leadership and strategic direction across multi-year, high-consequence programs to join our team in Albuquerque, NM. This senior role will own system architecture and engineering execution from concept maturation through fielding, drive cross-program technical decisions, and mentor engineering teams to deliver safe, effective, and affordable DE capabilities for the warfighter. Position responsibilities: Provide technical leadership and vision for directed energy system architectures, advancing technology roadmaps to meet near-term and future warfighter needs Act as the primary technical interface with senior customer stakeholders, program leadership, and external partners to translate operational needs and doctrine into capability-level requirements and measurable success criteria Lead development of high-level concepts of operation, mission use cases, and architecture trade studies that balance lethality, throughput, range, power/energy budgets, survivability, and cost </l

Sapience AI is the collective intelligence platform for professional communities. We sit above the CRMs, AMS platforms, and knowledge bases that organizations already run, and we turn the expertise scattered across them into something every member can search, act on, and share. The intelligence a community needs is already inside it. Most organizations just cannot reach it. Knowledge lives in silos, in legacy systems, in the heads of a few experts, and in fragmented records no one can connect. We change that. Our work is grounded in four commitments: technology elevates people and never replaces them, the best expertise is already inside the community, everything is built on trust, and every deployment is purpose-driven for the organization it serves. Let’s achieve more, together. Where this role sits This is the most senior individual-contributor architecture role at Sapience AI. You own how the whole system fits together: how the KO graph, the COGENT architecture, the models, the serving layer, and the product surface combine into one coherent, scalable, trustworthy platform. You work across every part of the stack, setting the architectural direction that lets specialized teams build fast without the system pulling apart at the seams. You are a force multiplier: not the owner of one area, but the person who makes sure all the areas add up to a platform that can carry Sapience AI’s ambitions for years. Why this role exists Collective intelligence spans hard subsystems: know

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an Hardware Emulation Architect on the HBM architecture team you will be responsible for architecting, enabling, and deploying hardware emulation capabilities for next generation HBM products. You will work with design, verification, firmware, and system teams to determine emulation needs and opportunities. You will drive the development of hardware emulation ecosystem including procurement of hardware emulation platforms, creation of emulation testbenches and transactors, and development of emulation friendly verification IP. You will be responsible for proactively developing emulation capabilities to meet the needs of current and future products. You will also lead the effort to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Responsibilities will include, but are not limited to: Develop and maintain hardware emulation environments for complex SoCs and subsystems. Compile, configure, and debug large-scale RTL designs on emulation platforms (e.g., Palladium, Veloce,