By submitting your resume, you’re expressing interest in our 2027 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with the local district office before applying for the role. Welcome to the world of NVIDIA, where innovation knows no…
Jobiba hiring network
Chip Level Defect Localization And Failure Analysis Engineer Jobs
359 active opportunities · Updated for October 2026
Fresh results
15 shown
Explore current chip level defect localization and failure analysis engineer jobs. Use filters to narrow by work mode, employment type, experience and date posted.
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era…
We are growing our team and looking for c
Technical Program Manager, Product Software at Tenstorrent in Austin, Texas, United States.
Summary: As a Design Verification Engineer Intern at Micron, you will collaborate with highly innovative design and verification teams to support the development of advanced DRAM and emerging memory technologies. This role offers hands-on exposure to high-density memory…
The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a…
Job Description: As a Design Engineer for Non-Volatile Memory Datapath Functional Group at Micron, you will support design and validation activities of Datapath and DDR high-speed interfaces of Flash Memory (non-volatile memory) products. Prior experience in Plane Datapath…
Role and Responsibilities Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level. Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check…
Role and Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time…
SoC Timing (Static Timing Analysis/STA) Engineer, HBM at Micron in United States. Full-time · On-site.
About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and…
Senior Engineer- DEG Layout at Micron in Bengaluru, KA, India. Full-time · On-site.
As a Staff/Principal Design Engineer in the NVE Design Engineering organization at Micron Technology, Inc., you will drive the transformation of NAND circuit development through design automation, agentic circuit-design enablement, and environment transition! Implementing core…
In this challenging role you will be engaged block level and sub-system level design and timing optimization and supervising their layout. You will be also partnering with the Logic Team to explain and support the array functionality. You will collaborate with project teams to…
Get new chip level defect localization and failure analysis engineer jobs by email
Daily job updates · Unsubscribe anytime