Semiconductor Equipment Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description We develop advanced memory technologies that transform how the world uses information to enrich life for all. As a Design Engineer, you will craft and optimize digital, analog, and memory circuits while collaborating with global design and verification teams. You will build solutions that improve quality, reliability, manufacturability, and product performance while continuing to learn and innovate in a global engineering environment! Responsibilities Design, develop, and optimize memory, logic, and analog circuits for new memory products. Perform circuit validation, parasitic modeling, reticle experiments, and tape-out revisions to drive performance and manufacturing efficiency . Lead layout activities including floorplanning, placement, routing, verification, modeling, and simulation using industry-standard tools. Collaborate across Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to solve technical challenges and support successful product execution. Drive innovation in future memory technologies while building design quality and standardization across global engineering teams. Minimum Qualifications Bachelor’s degree or equivalent experience in Electrical Engineering, Electronic Engineering, or a related field, with 10+ years of relevant industry experience; or a master’s degree with 7+ years; or a Ph.D. with 5+ years of relevant industry experienc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, our vision is to transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, Micron develops technologies that accelerate the transformation of information into intelligence. The DRAM Engineering Group (DEG) creates advanced memory solutions that enable modern applications, including artificial intelligence, high-performance computing, and immersive user experiences. Our team fosters innovation, collaboration, integrity, and continuous learning while solving some of the industry’s most complex engineering challenges. The Semiconductor Design Engineer will contribute to the design, simulation, optimization, and validation of digital and analog CMOS circuits for advanced DRAM and emerging memory technologies. This role provides opportunities to work across the full product lifecycle, from early technology development through product qualification, while collaborating with global design, verification, and manufacturing teams. The successful candidate will develop technical expertise in memory design, circuit analysis, and design automation while supporting the delivery of high-quality products. Responsibilities Design, simulate, analyze, and optimize CMOS memory circuits and functional blocks, including memory arrays, control logic, datapaths, address decoding, and input/output interfaces. Support physical design activities such as floor planning, placement, routing optimization, layout verification, and manufacturability improvements.

New College Grad - Semiconductor Design Engineer, DRAM Products Group — Boise, ID - Main Site. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Summary The Senior Director, Semiconductor Sourcing and NPI Procurement leads the global strategy, sourcing, and supplier ecosystem for wafer foundry services, IP and EDA services, discrete actives semiconductors, and 3rd party NAND flash controller categories as well as the New Product Introduction Procurement function. This role is accountable for delivering cost competitiveness, supply assurance, and long-term resilience across a complex semiconductor value chain. Partnering closely with engineering, manufacturing, and business leaders, the role drives category strategies, supplier performance, and risk mitigation at category and product level while enabling Micron’s growth and innovation priorities. Success in this role requires deep semiconductor domain expertise, strong commercial acumen, and the ability to lead large, global teams to deliver enterprise-level outcomes. Main Responsibilities Define and execute global procurement strategies for wafer foundry services, IP and EDA ser

WHAT IS BOX? Box (NYSE:BOX) is the leader in Intelligent Content Management. Our platform enables organizations to fuel collaboration, manage the entire content lifecycle, secure critical content, and transform business workflows with enterprise AI. We help companies thrive in the new AI-first era of business. Founded in 2005, Box simplifies work for leading global organizations, including JLL, Morgan Stanley, and Nationwide. Box is headquartered in Redwood City, CA, with offices across the United States, Europe, and Asia. By joining Box, you will have the unique opportunity to continue driving our platform forward. Content powers how we work. It’s the billions of files and information flowing across teams, departments, and key business processes every single day: contracts, invoices, employee records, financials, product specs, marketing assets, and more. Our mission is to bring intelligence to the world of content management and empower our customers to completely transform workflows across their organizations. With the combination of AI and enterprise content, the opportunity has never been greater to transform how the world works together and at Box you will be on the front lines of this massive shift. WHY BOX NEEDS YOU As an Enterprise Sales Director, you will lead a team of Account Executives that focus on closing pivotal deals in accounts experiencing high growth within the High Tech and Semiconductor verticals. You will join a team of highly motivated sales professionals that take pride in landing new customers, running strategic sales cycles and delivering the Box message to a wide base of accounts across various industries. WHAT YOU'LL DO Hire, train, and manage a team of Enterprise Account Executives Develop Account Executives for career growth within the Box Sales organization Support team in customer on-sites, calls, and meetings Report on sales metrics and forecast to Senior Sales Management Motivate team to exceed objectives throug

半導体エンジニア（2026・2027年卒／既卒歓迎）｜Semiconductor Engineer – Class of 2026/2027 & Recent Graduates — Hiroshima - Fab 15, Japan. Apply via Workday.

What We’re Looking For: We’re looking for verification engineers to contribute to and own blocks, sub-systems and potentially the entire wafer-level and cluster-level verification. Ideal Background: Ideal candidates will have: Experience owning verification of blocks and/or sub-systems in SoCs Experience driving verification for complex processor or high performance ASIC designs Experience with performance verification Nice to Have: Experience owning verification of an entire chip or SoC Experience owning verification of a multi-die/multi-chiplet/MCM design Experience in verification of networks, especially multi-network interfaces

What We’re Looking For: We’re looking for DFT engineers to contribute to and own DFT efforts for blocks and entire dies on the A-0 and A-1 wafer-scale systems. Ideal Background: Experience leading DFT efforts for multiple advanced node SoC tapeouts Nice to Have: Experience leading DFT efforts for large die area (eg reticle-max) chips Experience leading DFT efforts for multi-die/multi-chiplet/MCM designs Experience leading DFT efforts for AI accelerator SoCs

What We’re Looking For: We’re looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations. Ideal Background: An ideal candidate will have: Experience with full ownership of the specs and drove implementation for at least one SoC/die A deep understanding of the process of architecture, microarchitecture and physical design and the ability to coordinate with various groups to drive implementation of SoCs Understanding of SoC interactions with packages, memory subsystems and IO, and ability to work with teams who are responsible for said interacting blocks Nice to Have: Experience with multi-die/multi-chiplet/MCM designs Experience with reticle-max/large-die SoC architecture Understanding of levers available for improving PPA Track record of very high speed A0 silicon delivery

What We’re Looking For: We’re looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in-house and outsource, and then managing the outsourced process and integrating it with the in-house flow and effort. Ideal Candidates: Ideal candidates will have: Hands-on experience with the physical design process for at least one block in multiple advanced node tapeouts Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change the RTL to improve/fix them Experience both with in-house and outsourced physical design flows Nice to Have: Experience with physical design process for multi-die/multi-chiplet/MCM designs Experience with physical design process for reticle-max or near reticle max designs Experience with very high power density chips Experience with the physical design process for AI chips Experience with the physical design process of analog and mixed signal blocks and macros

What We’re Looking For: We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal Background: An ideal candidate will have: Hands-on experience with multiple advanced node tapeouts Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts Understanding of PPA improvement and what levers exist for each level of the stack Ability to think creatively about methodology for fast design iterations Nice to Have: Hands-on experience with ASIC design process for large die (ideally reticle max) chips Hands-on experience with ASIC design process for AI chips Hands-on experience with multi-die/multi-chiplet/MCM designs

What We’re Looking For: We’re looking for architects to own key blocks on the A-0 and A-1 systems. This is a role with ownership of an entire sub-block, and you will need to understand how it fits into the entire system and work with other architects and architecture leaders to integrate it into the broader system. Ideal Background: Hands-on experience in owning and delivering the architecture of a block that was part of a larger chip/system. Understanding and hands-on experience in the design of AI accelerators Experience working with microarchitects in the implementation and verification of said block Nice to Have: Experience with the physical design process of the block you owned Experience with large die area chips Experience with multi-die and multi-package chips and systems

What We’re Looking For: We’re looking for memory subsystem architects to contribute and own aspects of the memory subsystem for the largest and highest bandwidth memory system ever built to date. This includes the distributed memory fabric, memory controllers, interface with the XPUs/compute complex, etc. Ideal Candidates: Ideal candidates will have: Deep knowledge and hands-on experience in the design and implementation of memory sub-systems Understand LLM inference workloads and what the impact of that for the memory subsystem is Understand the benefits and limitations of memory tiering for various workloads Nice to Have: Experience with CXL and other memory pooling protocols Experience with design and implementation of memory controllers Experience with processing in memory and other “unique” memory subsystem projects and efforts

What We’re Looking For: We’re looking for an architect to lead the design and implementation of the inter-wafer scale-up network. Connecting very high bandwidth and high capacity wafers into a “super-system” will enable previously unprecedented capabilities for the AI industry. Ideal Background: Deep knowledge of networks, especially knowledge of tradeoffs and advantages of different network topologies for different workloads and applications Understanding and ideally experience in implementation of network protocols Understanding of AI workloads and their network design implications (eg message sizes vs latency, bandwidth, hops, etc) Nice to Have: Hands-on experience with architecture and design process of either switch or NIC chips Hands-on experience designing AI networks Experience in tradeoffs between different network protocols for AI applications Experience in large-scale AI clusters Experience in large-scale optical network fabrics, especially with issues around reliability/RAS

What We’re Looking For: We’re looking for engineers to contribute to the thermomechanical, electrical and mechanical design and assembly of the IO modules that attach to our A-0 and A-1 wafers. Ideal Background: Deep understanding and hands-on experience with signal integrity signoff for copper and electro-optic connector interfaces Hands-on experience with mechanical aspects of electrical and electro-optic connectors Experience with bringup of connectorized links and systems Nice to Have: Experience and understanding of sockets and socketed connectors Experience with co-packaged copper and co-packaged optics Experience with high density optical modules Experience with XPO optical pluggable form factors